发布求助
文献互助 智能选刊 最新文献

2021 IEEE 14th International Conference on ASIC (ASICON)最新文献

筛选
英文 中文
A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC 一种300MS/s的5位高线性、二进制重组冗余Sub-SAR ADC, 14位流水线式sar ADC
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620444
Guoyao Wu, Ziwei Li, Yutong Zhao, Fan Ye, Junyan Ren
{"title":"A 5-bit High-Linearity, Binary-Recombination-Redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC","authors":"Guoyao Wu, Ziwei Li, Yutong Zhao, Fan Ye, Junyan Ren","doi":"10.1109/ASICON52560.2021.9620444","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620444","url":null,"abstract":"The paper presents a 5-bit high-linearity, binary-recombination-redundancy Sub-SAR ADC in 300MS/s, 14-bit Pipelined-SAR ADC in TSMC 28nm process. The highlight of the paper is the proposed high-linearity Sub-SAR ADC using binary recombination redundancy technique with high-speed SAR logic. In addition, the proposed high-speed SAR logic is energy-efficient. In this paper, the requirement proposed by C. Liu in 2015 is reconsidered, and after experimental simulation, a new requirement of the recombination capacitor cells removed from the MSB or sub-MSB is presented. It should satisfy the sum of a combination of the power-of-2 number of B, instead of the power-of-2 number of B. At 0.9V supply and 300MS/s, the proposed Sub-SAR ADC consumes 1.62mW, using a sampling capacitor array of 1.92pF at the input sine wave of ±0.3V. It achieves SNDR of 75.5dB and SNDR of 74dB at low and Nyquist frequency respectively, while the 3-stage pipelined-SAR ADC using the proposed Sub-SAR ADC finally achieves SNDR of 64.3dB, and SNDR of 64dB at low and Nyquist frequency, respectively. The whole ADC consumes 9.4mW, achieving FoMs of 166dB, or FoMw of 24.3fJ/conv.-step.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126884724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch 超低电压低功耗自适应静态脉冲锁存器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620378
Peiyi Zhao, Zisong Wang, Congyi Zhu, Tom Springer, Jacob Anabi, Yinshui Xia, Lingli Wang
{"title":"Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch","authors":"Peiyi Zhao, Zisong Wang, Congyi Zhu, Tom Springer, Jacob Anabi, Yinshui Xia, Lingli Wang","doi":"10.1109/ASICON52560.2021.9620378","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620378","url":null,"abstract":"Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption in processors. In this paper, a novel Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch, SSPL, is proposed. In terms of power consumption, SSPL outperforms prior state-of-the-art pulsed latch up to 60.1% at 10% data switching activity using 1V in a 45nm technology.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114626276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hardware Design of Gaussian Kernel Function for Non-Linear SVM Classification 非线性支持向量机分类中高斯核函数的硬件设计
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620361
Yuanfa Wang, Yu Pang, Huan Huang, Qianneng Zhou, Jiasai Luo
{"title":"Hardware Design of Gaussian Kernel Function for Non-Linear SVM Classification","authors":"Yuanfa Wang, Yu Pang, Huan Huang, Qianneng Zhou, Jiasai Luo","doi":"10.1109/ASICON52560.2021.9620361","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620361","url":null,"abstract":"High-performance implementation of non-linear support vector machine (SVM) function is important in many applications. This paper develops a hardware design of Gaussian kernel function with high-performance since it is one of the most modules in non-linear SVM. The designed Gaussian kernel function consists of Norm unit and exponentiation function unit. The Norm unit uses fewer subtractors and multiplexers. The exponentiation function unit performs modified coordinate rotation digital computer algorithm with wide range of convergence and high accuracy. The presented circuit is implemented on a Xilinx field-programmable gate array platform. The experimental results demonstrate that the designed circuit achieves low resource utilization and high efficiency with relative error 0.0001.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116324982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Energy-Efficient Image Denoising Accelerator with Depth-wise Separable Convolution and Fused-Layer Architecture 基于深度可分离卷积和融合层结构的高效图像去噪加速器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620485
Xuyang Duan, Ruiqi Xie, Jun Han
{"title":"An Energy-Efficient Image Denoising Accelerator with Depth-wise Separable Convolution and Fused-Layer Architecture","authors":"Xuyang Duan, Ruiqi Xie, Jun Han","doi":"10.1109/ASICON52560.2021.9620485","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620485","url":null,"abstract":"Image denoising is an important low-level vision task, which has been widely studied to reduce the noise in images. Denoising methods based on deep learning have achieved great performance improvement. However, the huge computation requirements of these methods prevent their application in practical scenarios. Moreover, the hardware accelerator of deep learning denoising methods has rarely been studied. Therefore, we optimize DnCNN for additive white Gaussian noise (AWGN) to obtain the hardware-friendly Light-DnCNN and design an energy-efficient denoising accelerator based on Light-DnCNN. The accelerator has a denoising frame rate of 19.9 FPS with 3.52 W. Its energy efficiency is 5 times and 1319 times higher than that of Titan X GPU and Intel i7-9700 CPU respectively.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121546951","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Three-valued Adder Circuit Implemented in ZnO Memristor with Multi-resistance States 在多电阻状态ZnO忆阻器中实现的三值加法器电路
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620275
Zhixin Wu, Yuejun Zhang, Shimin Du, Zhecheng Guo, Wanlong Zhao
{"title":"A Three-valued Adder Circuit Implemented in ZnO Memristor with Multi-resistance States","authors":"Zhixin Wu, Yuejun Zhang, Shimin Du, Zhecheng Guo, Wanlong Zhao","doi":"10.1109/ASICON52560.2021.9620275","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620275","url":null,"abstract":"The memristors are widely used in-memory computation due to their advantages such as high integration density, fast read/write speed, non-volatile storage and low power consumption. By adjusting the conversion between the multi-resistance states of the memristor, the ternary logic with larger information processing capacity can be realized with simple operation and circuit design. In this paper, we fabricated a Pt/ZnO/Pt memristor, which shows the characteristics of multi-resistance states conversion in multiple cycle operations, further realized the complete set of ternary logic based on the ZnO-based memristor, and designed a three-valued adder unit circuit with potential application value of full memristor. The result shows that the function of a three-valued adder can be realized by using five memristors. Compared with the traditional CMOS circuit, the three-valued adder unit circuit based on memristor reduces the number of components by one third. This approach is helpful for building future high-performance computer architectures.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125844608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Novel Power PiN Diode with p-type Schottky Anode and Trench Oxide for Improving Reverse Recovery 基于p型肖特基阳极和沟槽氧化物的新型功率引脚二极管
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620530
Weidan Li, Mingmin Huang, Yun Li, Zhimei Yang, M. Gong
{"title":"A Novel Power PiN Diode with p-type Schottky Anode and Trench Oxide for Improving Reverse Recovery","authors":"Weidan Li, Mingmin Huang, Yun Li, Zhimei Yang, M. Gong","doi":"10.1109/ASICON52560.2021.9620530","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620530","url":null,"abstract":"A novel power diode with p-type schottky anode and trench oxide is proposed. The p-type schottky anode is able to reduce the reverse recovery charge (Qrr). The trench oxide regions with n-rings separate n+ cathode regions from p-type cathode (pc) regions. The n-rings stop the electric field to ensure a fluent electron leakage current path from the n+ cathode region to n-rings in the blocking state, which eliminates the effect of pc regions on the breakdown voltage (VB). Moreover, pc regions can inject holes into the n-drift region during reverse recovery, which helps to obtain soft reverse recovery. Simulations of 1300 V designs show that the proposed PiN diode is able to reduce Qrr by 50% and effectively suppress electrical oscillations during reverse recovery.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122268359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Four Modes and Smooth Transition Non-inverting Buck-Boost Converter 四模平滑过渡非反相Buck-Boost变换器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620338
Chengzhi Xu, Lianxi Liu
{"title":"A Four Modes and Smooth Transition Non-inverting Buck-Boost Converter","authors":"Chengzhi Xu, Lianxi Liu","doi":"10.1109/ASICON52560.2021.9620338","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620338","url":null,"abstract":"This paper presents a DC-DC converter circuit with four operation modes which can be used for energy harvesting in the IoT. When the input voltage varies in a wide range, the circuit is not disturbed and smooth transition is achieved. It is implemented in SMIC 0.18 um CMOS process and the Cadence Spectre simulation tool is used for system-level and module circuit simulation verification. The simulation results show that the converter operates with a wide input voltage range from 0.4V to 3.3V, 1.8V output voltage, maximum load current of 100mA and switching frequency of 1MHz.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127920442","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
E/D Mode Logic Cells and Series-to-Parallel Interface with Less Transistors and Better Structure Consistence in GaAs Process GaAs制程中E/D模式逻辑单元与串联-并行接口，晶体管少，结构一致性好
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620443
Shijie Chen, T. Yang, Xiang Li, Jian Yang, Liang Qi, Yong Wang
{"title":"E/D Mode Logic Cells and Series-to-Parallel Interface with Less Transistors and Better Structure Consistence in GaAs Process","authors":"Shijie Chen, T. Yang, Xiang Li, Jian Yang, Liang Qi, Yong Wang","doi":"10.1109/ASICON52560.2021.9620443","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620443","url":null,"abstract":"E/D mode logic cells and a series-to-parallel interface are reported in this work. The proposed logic cells present less transistor elements as well as better structure consistence as compared to other classical reports. With these logic cells, a series-to-parallel interface circuit is prototyped and post-simulated. It presents benefit on making targeted compromises for anti-interference capability, area and operating frequency of the transceiver according to transceiver design index.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133974996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and Implement of Median Filter toward Remote Sensing Images Based on FPGA 基于FPGA的遥感图像中值滤波设计与实现
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620528
Yalong Pang, Shuai Jiang, Bowen Cheng, Weiwei Liu, Yuhang Wu
{"title":"Design and Implement of Median Filter toward Remote Sensing Images Based on FPGA","authors":"Yalong Pang, Shuai Jiang, Bowen Cheng, Weiwei Liu, Yuhang Wu","doi":"10.1109/ASICON52560.2021.9620528","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620528","url":null,"abstract":"In this paper, an improved median filtering algorithm for remote sensing images is proposed and implemented on FPGA. According to the characteristics of FPGA parallel processing, the 5x5 double-sorted median filtering algorithm is optimized, and the 3x3 double-sorted median filtering, 5x5 double-sorted median filtering and bit-level median filtering are implemented by pipelining, which improves the frequency and speed. The final simulation results show that the maximum clock frequency of this design on XC7K325T can reach 419MHz. For remote sensing images of 4096x4096 size, the processing of a single image can spend 40ms, and the throughput rate is 25 images/second, which can meet the requirements of on-orbit real-time processing and can be applied in practice.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"73 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131818900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On-Chip Filter for Mitigating EMI-Related Common-Mode Noise in High-Speed PAM-4 Transmitter 抑制高速PAM-4发射机中emi相关共模噪声的片上滤波器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620447
Zi-Ming Liu, Rehan Azmat, Xin-Yue Liu, Li Wang, C. Yue
{"title":"On-Chip Filter for Mitigating EMI-Related Common-Mode Noise in High-Speed PAM-4 Transmitter","authors":"Zi-Ming Liu, Rehan Azmat, Xin-Yue Liu, Li Wang, C. Yue","doi":"10.1109/ASICON52560.2021.9620447","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620447","url":null,"abstract":"The electromagnetic interference (EMI) is generated by the common-mode (CM) noise in differential circuits and has a high risk of degrading other circuits’ performance by radiating the disturbance. This paper demonstrates an on-chip filter that suppresses the CM noise while keeping the integrity of the differential-mode (DM) signal. Based on the delay equalizer, this filter provides the benefit of whole spectrum DM constant resistance, which achieves great matching between the off-chip transmission line and the on-chip circuit. The simulation results show that the filter efficiently mitigates the EMI of a 56 Gbps PAM-4 transmitter by suppressing the CM noise up to 18.85 dB at 28 GHz with core area of 207 μm × 125 μm.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"259 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133695195","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信