E/D Mode Logic Cells and Series-to-Parallel Interface with Less Transistors and Better Structure Consistence in GaAs Process

Abstract

E/D mode logic cells and a series-to-parallel interface are reported in this work. The proposed logic cells present less transistor elements as well as better structure consistence as compared to other classical reports. With these logic cells, a series-to-parallel interface circuit is prototyped and post-simulated. It presents benefit on making targeted compromises for anti-interference capability, area and operating frequency of the transceiver according to transceiver design index.