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2021 IEEE 14th International Conference on ASIC (ASICON)最新文献

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A Self-regulating Dynamic Reference Sensing Scheme with Balanced Trade-Off between Read Disturbance and Sensing Margin 一种读取干扰与感知余量平衡的自调节动态参考感知方案
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620248
Jia-le Cui, Haibing Wang, Hao Cai
{"title":"A Self-regulating Dynamic Reference Sensing Scheme with Balanced Trade-Off between Read Disturbance and Sensing Margin","authors":"Jia-le Cui, Haibing Wang, Hao Cai","doi":"10.1109/ASICON52560.2021.9620248","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620248","url":null,"abstract":"Spin transfer torque MRAM (STT-MRAM) is a promising candidate for next-generation memory thanks to its high endurance and non-volatility. In low-power scenario, MRAM sensing margin is degraded due to the limited reading current, which makes read operation difficult. This paper proposes a novel self-regulating dynamic reference (SRDR) sensing scheme to alleviate sensing bit-error rate (BER). The proposed scheme optimizes the conventional dynamic reference generator so that the gain and bias of the attenuator can be adaptively changed according to the bit-line voltage. The proposed scheme is evaluated with 65-nm CMOS. Simulation results show significant improvement. Compared with the previous dynamic dual-reference sensing scheme, the proposed scheme improves the sensing margin by 103% at a lower read current (10.09μA, only 18% of the critical switching current) and reduces the BER from 3.5E-02 to 9.6E-06.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133724553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
TCAD simulation of trench-gate IGBTs for prediction of carrier lifetime requirements for future scaled devices 沟栅igbt的TCAD仿真，用于预测未来缩放器件的载波寿命要求
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620503
M. Watanabe
{"title":"TCAD simulation of trench-gate IGBTs for prediction of carrier lifetime requirements for future scaled devices","authors":"M. Watanabe","doi":"10.1109/ASICON52560.2021.9620503","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620503","url":null,"abstract":"Silicon trench-gate insulated gate bipolar transistors (IGBTs) were analyzed using technology CAD (TCAD). Excellent agreement was confirmed between the JC-VCE characteristics obtained by 3D-TCAD simulations and experiments. The carrier lifetime requirement for scaled trench-gate IGBTs was determined by extraction of the on-resistance of the n-base layer derived from the electric potential profile.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133443222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of Switching Characteristics of Wide SOA and High Reliability 100 V N-LDMOS Transistor with Dual RESURF and Grounded Field Plate Structure 宽SOA高可靠性100 V N-LDMOS双路复路接地结构晶体管开关特性分析
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620319
A. Kuwana, Jun-Ichi Matsuda, Haruo Kobayashi
{"title":"Analysis of Switching Characteristics of Wide SOA and High Reliability 100 V N-LDMOS Transistor with Dual RESURF and Grounded Field Plate Structure","authors":"A. Kuwana, Jun-Ichi Matsuda, Haruo Kobayashi","doi":"10.1109/ASICON52560.2021.9620319","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620319","url":null,"abstract":"We proposed a wide SOA and high reliability 0.35 μm CMOS compatible 100 V dual RESURF LDMOS transistor with low switching loss and low specific on-resistance for automotive applications. This paper describes detailed switching characteristics by changing load resistance RL and gate resistance RG for actual use which were not investigated. TCAD simulations verified that the total energy loss (total switching loss + conduction loss) of the proposed device is sufficiently smaller (about 30 % down at the maximum) than that of the conventional device in most of the actual use range except for the following region: low duty cycle D < 0.1 and high switching frequency f > 1.1 MHz at a low RG of 1.31 Ωmm2 and a high RL of 65.5 Ωmm2 under a device layout area of 1 mm2. Also, a unique switching characteristic of the proposed device, or a convex-shape gate plateau, not observed before, is analyzed.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132592276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Large Coercive Field in Hf0.5Zr0.5O2-based Capacitors with Gd Top Electrode Gd顶电极hf0.5 zr0.5 o2电容器的大矫顽场研究
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620386
Xiaoyue Zhao, M. Shao, Houfang Liu, R. Zhao, Xichen Sun, Xiao Liu, Xiaoming Wu, Yi Yang, T. Ren
{"title":"Large Coercive Field in Hf0.5Zr0.5O2-based Capacitors with Gd Top Electrode","authors":"Xiaoyue Zhao, M. Shao, Houfang Liu, R. Zhao, Xichen Sun, Xiao Liu, Xiaoming Wu, Yi Yang, T. Ren","doi":"10.1109/ASICON52560.2021.9620386","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620386","url":null,"abstract":"Gd top electrode was applied in the Hf<inf>0.5</inf>Zr<inf>0.5</inf>O<inf>2</inf> (HZO)-based capacitors via re-capping technique and its ferroelectric characteristics were investigated. A recorded-highest positive coercive field value of ~3.02 MV/cm was demonstrated with a P<inf>r</inf> value near 11.1 μC/cm<sup>2</sup>. The asymmetric switching dynamics of the Pt/Gd/HZO/TiN capacitor were studied to confirm the origin of the large E<inf>c</inf>. This work will contribute to the future applications of Gd electrodes in ferroelectric memory transistors.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130105535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Knowledge Distillation for U-Net Based Image Denoising 基于U-Net的图像去噪知识蒸馏
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620364
Wenshu Chen, L. Peng, Yujie Huang, Ming-e Jing, Xiaoyang Zeng
{"title":"Knowledge Distillation for U-Net Based Image Denoising","authors":"Wenshu Chen, L. Peng, Yujie Huang, Ming-e Jing, Xiaoyang Zeng","doi":"10.1109/ASICON52560.2021.9620364","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620364","url":null,"abstract":"In recent years, algorithms based on convolutional neural networks (CNNs) have shown great advantages in image denoising. However, the existing state-of-the-art (SOTA) algorithms are too computationally complex to be deployed on embedded devices, like mobile devices. Knowledge distillation is an effective model compression method. However, researches on knowledge distillation are mainly on high-level visual tasks, like image classification, and few on low-level visual tasks, such as image denoising. To solve the above problems, we propose a novel knowledge distillation method for the U-Net based on image denoising algorithms. The experimental results show that the performance of the compressed model is comparable with the original model in the case of quadruple compression.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130275637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
EG-HRNet: An Efficient High-Resolution Network Using Ghost-Modules for Human Pose Estimation EG-HRNet:一种高效的高分辨率网络，使用幽灵模块进行人体姿势估计
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620383
Yiting Wang, Zhenyin Zhang, Gengsheng Chen
{"title":"EG-HRNet: An Efficient High-Resolution Network Using Ghost-Modules for Human Pose Estimation","authors":"Yiting Wang, Zhenyin Zhang, Gengsheng Chen","doi":"10.1109/ASICON52560.2021.9620383","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620383","url":null,"abstract":"As an essential task in predicting a human’s behavior, human pose estimation (HPE) plays a very important role in many real-time applications. However, existing HPE methods are still too large which severely prevents them to be used in resource-sensitive applications. In this paper, aiming to a significant reduction in computation complexity, we propose an efficient high-resolution HPE network using ghost-modules (EG-HRNet). Based on the HRNet architecture, the new EG-HRNet uses modified shuffle blocks as the inner blocks to replace the residual blocks. Meanwhile, we use the lightweight ghost bottleneck for a more efficient feature extraction and use the ghost modules in the fusion layers to replace the costly 1x1 point-wise convolutions. Finally, we use the distribution-aware coordinate representation of the keypoints to acquire more accurate heatmaps of the input images. The experimental results on the COCO keypoint detection dataset show that the new efficient EG-HRNet model has successfully reached a tender balance between the processing speed and the estimation accuracy.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"20 14","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113979701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Etch Scheme to Form Sloped Profile by Standard Anisotropic CMOS Process 一种利用标准各向异性CMOS工艺形成倾斜轮廓的新型蚀刻方案
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620422
Ming Li, Xiaoxu Kang, Xiaolan Zhong
{"title":"A Novel Etch Scheme to Form Sloped Profile by Standard Anisotropic CMOS Process","authors":"Ming Li, Xiaoxu Kang, Xiaolan Zhong","doi":"10.1109/ASICON52560.2021.9620422","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620422","url":null,"abstract":"In this work, electrical short problem was found for sensing material resistor device, which was defined by thin metal electrode layer pattern. FIB and X-SEM was done for failure analysis (FA), and thin metal layer residue was found on the sidewall bottom of the sensing material pattern edge which had induced the short problem. Mechanism of the residue problem was investigated, and it was because that metal layer thickness on the sidewall of sensing material pattern edge was much larger than thin metal layer thickness on top surface which had induced that metal layer residue on sidewall during anisotropic etch process. Novel etch scheme was proposed and implemented to realize sloped profile with large angle and solve this problem. Physical profile and electrical test was done to evaluate the performance of the new process. From the measured data, the new process scheme can well solve the short problem.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114159259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A split-gate SiC trench MOSFET with embedded unipolar diode for improved performances 一种内嵌单极二极管的分栅SiC沟槽MOSFET
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620233
Zheng Wu, Chao Xia, B. Yi, Junji Cheng, Haimeng Huang, M. Kong, Hongqiang Yang, Wenkun Shi
{"title":"A split-gate SiC trench MOSFET with embedded unipolar diode for improved performances","authors":"Zheng Wu, Chao Xia, B. Yi, Junji Cheng, Haimeng Huang, M. Kong, Hongqiang Yang, Wenkun Shi","doi":"10.1109/ASICON52560.2021.9620233","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620233","url":null,"abstract":"In this paper, a split-gate SiC trench MOSFET (SG-TMOS) with embedded unipolar diode for reverse conduction is proposed. By introducing the split-gate, an embedded MOS-channel diode is formed during the reverse conducting state, and helps to reduce the on-state voltage drop to 1.87 V, which is ~30% reduced compared with that of the conventional trench/planar MOSFET (C-TPMOS). Besides, the dynamic performances of the SG-TMOS are significantly improved. The CGD and CGS decrease by 80.3% and 35.2% compared with that of the C-TPMOS. As a result, the total switching loss (Etot) is reduced by 39.4% compared to that of the C-TPMOS.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114453893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A High Efficiency Re-configurable Step-down Switched Capacitor DC-DC Converter for Medical Implants Application 用于医疗植入物的高效可重构降压开关电容DC-DC变换器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620516
Qianhui Fan, Wensi Wang, Xu Liu, Qiang Gao, Shuqin Geng
{"title":"A High Efficiency Re-configurable Step-down Switched Capacitor DC-DC Converter for Medical Implants Application","authors":"Qianhui Fan, Wensi Wang, Xu Liu, Qiang Gao, Shuqin Geng","doi":"10.1109/ASICON52560.2021.9620516","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620516","url":null,"abstract":"In this paper, a re-configurable switched-capacitor DC-DC converter which features high efficiency, small silicon area and low voltage ripple is designed. The switched-capacitor based converter has inherently superior counter electromagnetic interference (EMI) capability, which is important for medical implants. This converter utilizes a self-adaptation mechanism to switch between normal pulse frequency modulation (PFM) and SKIP modes. This mechanism optimizes the power consumption by shielding part of the clock to based on load current conditions. Simulation results show that the output voltage settles around 2.4V with +1.6/-5% error when the input voltages are 2.5V, 3.7V, and 4.9V, respectively. Peak efficiency of 97% and average efficiency of 93% have been achieved in normal mode 2-15mA load current. For light load, i.e.<2mA load, the efficiency of SKIP mode has been improved. The SC converter IC is then implemented in a 180 nm 5V standard CMOS process.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"235 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132213933","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Adaptive OCD and ODT Control for Channel S/I Enhancement in DDR4 SDRAM DDR4 SDRAM中信道S/I增强的自适应OCD和ODT控制
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620294
Yanwu Du, Chris Eom, Jake Jung, Brian Lee, Edwin Kim, Kanyu Cao
{"title":"Adaptive OCD and ODT Control for Channel S/I Enhancement in DDR4 SDRAM","authors":"Yanwu Du, Chris Eom, Jake Jung, Brian Lee, Edwin Kim, Kanyu Cao","doi":"10.1109/ASICON52560.2021.9620294","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620294","url":null,"abstract":"This paper presents a new method to enhance DRAM memory interface performance. To achieve bigger eye diagram during read and write operation, output driver’s impedance is needed to be controlled respectively. For example, the low output driver’s impedance makes bigger eye during read operation, but the high output driver’s impedance makes bigger eye during write operation. To solve this problem, adaptive OCD and ODT control scheme is presented in this paper. Adopting the adder and subtracter in front of pre-driver inside each DQ block and controlled by read or write command flag, output driver’s impedance can be controlled, during read and write operation, respectively. The proposed scheme enhances 20% voltage margin and 10% timing margin during read operation and 20% voltage margin and 15% timing margin during write operation.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128588489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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