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2021 IEEE 14th International Conference on ASIC (ASICON)最新文献

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A ReRAM-based 10T2R SRAM Using Power-off Recovery Function for Reducing Power 基于rram的10T2R SRAM，采用掉电恢复功能降低功耗
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620274
Sheng Dai, Yuejun Zhang, Huihong Zhang, Jing Li, Ye Lin
{"title":"A ReRAM-based 10T2R SRAM Using Power-off Recovery Function for Reducing Power","authors":"Sheng Dai, Yuejun Zhang, Huihong Zhang, Jing Li, Ye Lin","doi":"10.1109/ASICON52560.2021.9620274","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620274","url":null,"abstract":"To solve the problem of power-off information loss of SRAM, non-volatile circuits are attracting more and more attention. However, there are some problems in the non-volatile circuit, such as long storage time and high-power consumption. In this paper, a scheme of 10T2R non-volatile SRAM use ReRAM is proposed. The 8T SRAM is selected for the high static noise margin (SNM). The addition of ReRAM provides the device with the ability to keep data after power-off and recover data after power-on. Then, the 2T2R structure of non-volatile memory uses a Memristive Voltage Divider (MVD) arrangement, not only saves the circuit area but also reduces the write energy. Finally, the functionality and performance of the ReRAM-based 10T2R SRAM are validated and evaluated in 65nm CMOS technology. The experimental results show that the non-volatile SRAM circuit has the power-off recovery function, and the restore latency needs 9ns. The restore yield of proposed circuit all achieve 100% when ReRAM R-ratio =10 and 20.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127272213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
High Precision AFE Design Methodology for Wearable EEG Acquisition 可穿戴式EEG采集高精度AFE设计方法
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620507
Chao Yuan, Ting Yi, Zhiliang Hong
{"title":"High Precision AFE Design Methodology for Wearable EEG Acquisition","authors":"Chao Yuan, Ting Yi, Zhiliang Hong","doi":"10.1109/ASICON52560.2021.9620507","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620507","url":null,"abstract":"Wearable electroencephalograph (EEG) acquisition sys-tem puts forward higher requirements for analog front-end (AFE) circuit, such as offset tolerance, common mode (CM) suppression, low noise and power consumption. This paper introduces design challenges and electrical characteristics of wearable EEG acquisition, reviews the two main system architectures, and focuses on different circuit techniques to improve key performance metrics, including large dynamic range (DR), high input impedance (Zin), low noise, CM and electrode offset rejection.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123434845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight 一种具有40.14 TOPS/W的半浮栅晶体管内存计算设计，用于频繁更新权值的矩阵乘法
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620271
Yukai Lin, Yu Wang, Xianwu Hu, Jiayun Feng, Gan Wen, Xiankui Xiong, Haidong Tian, Yufeng Xie
{"title":"A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight","authors":"Yukai Lin, Yu Wang, Xianwu Hu, Jiayun Feng, Gan Wen, Xiankui Xiong, Haidong Tian, Yufeng Xie","doi":"10.1109/ASICON52560.2021.9620271","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620271","url":null,"abstract":"To overcome the memory wall problem, in-memory computing (IMC) is proposed to accelerate matrix multiplication. While existing IMC designs encounter problems in scenes where weight updates frequently because of long latency of weight-update or short weight retention time. This paper proposes a semi-floating gate transistor (SFGT) based IMC design to improve the matrix-multiplication with frequently update weights. Simulation results shows that this design achieves access time of 5.32ns (1b IN/8b W) and energy efficiency of 40.14TOPS/W(1b IN/8b W). Besides, a SFGT IMC based solution combing weight-update with refreshing is proposed for matrix-multiplication and weight-update in multiple in multiple out (MIMO), a typical matrix-multiplication intensive scenes with frequently updated weight.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122727992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface 基于CNRZ-5的USR高速接口5-156.25Gb/s高引脚效率接收机
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620255
Zhang Geng, Fangxu Lv, Zhengbin Pang, Heming Wang, Dongbin Lv, Tao Liu, Jinwang Zhang
{"title":"A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface","authors":"Zhang Geng, Fangxu Lv, Zhengbin Pang, Heming Wang, Dongbin Lv, Tao Liu, Jinwang Zhang","doi":"10.1109/ASICON52560.2021.9620255","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620255","url":null,"abstract":"In order to improve the pin efficiency of the Die to Die (D2D)[1] interface, a CNRZ-5 coding based high speed receiver is proposed in this paper. To improve the signal quality of the receiver at high speed, a multi-input-comparator with equalization is introduced. In addition, a Forward Clock (FCK) structure with first-order data and clock recovery is used to reduce the power of the receiver. This D2D receiver is designed with 28nm CMOS process, and its power supply is 0.9 voltage. The simulation results show that, the receiver can work on 5-156.25Gb/s under a channel with maximum 7.5dB insertion loss at 156.25Gb/s. Furthermore, the receiver pin efficiency can be improved by 66.7% compared with other traditional differential signal receiver.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121825450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Single Photon Detector Readout Circuit Based on 0.18 μm CMOS Technology 基于0.18 μm CMOS技术的单光子探测器读出电路
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620527
Yunhao Fu, Zhongyuan Zhao, Hongbo Zhang, Jiaqi Jiang, Yu-Chi Chang
{"title":"A Single Photon Detector Readout Circuit Based on 0.18 μm CMOS Technology","authors":"Yunhao Fu, Zhongyuan Zhao, Hongbo Zhang, Jiaqi Jiang, Yu-Chi Chang","doi":"10.1109/ASICON52560.2021.9620527","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620527","url":null,"abstract":"Single photon detection is currently the key technology in the fields of lidar and three-dimensional imaging. Avalanche photodiode has attracted widespread attention due to their low power consumption, high quantum efficiency, and high speed response characteristics. This paper designs a readout circuit based on a single-photon avalanche diode. The system adopts the active quenching and active recovery front-end circuit, and realizes the avalanche detection threshold voltage adjustment through the 4-bit digital-to-analog converter. In order to reduce the influence of noise, the front-end circuit adopts a gated operating mode, and realizes hold-off time adjustment through a monostable flip-flop, so that the minimum dead time reaches 20 ns. The system has two functions: photon counting and TOF ranging, which are realized by 18-bit asynchronous counter and two-level time-to-digital converter respectively. Corresponding encoding rules are designed for the abnormal conditions of edge sampling. At 500MHz clock frequency, TDC accuracy can reach 250 ps. The system has been designed and implemented in 0.18 μm standard CMOS technology, and the pixel circuit area is 155 μm×155 μm.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122087747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Advances in Continuous-time MASH ΔΣ Modulators 连续时间MASH ΔΣ调制器的研究进展
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620480
Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, G. Shi, Guoxing Wang
{"title":"Advances in Continuous-time MASH ΔΣ Modulators","authors":"Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, G. Shi, Guoxing Wang","doi":"10.1109/ASICON52560.2021.9620480","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620480","url":null,"abstract":"The maximum clock frequency of oversampled continuous-time (CT) delta sigma modulators (DSM) has increased significantly over the past decade, showing larger bandwidth capacity than their discrete-time counter parts. On the other hand, under a large clock rate,","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"170 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123312784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Process Optimization for CMOS Compatible MEMS Capacitive Acoustic Sensor CMOS兼容MEMS电容式声传感器工艺优化
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620398
Ming Li, Xiaoxu Kang, Xiaolan Zhong
{"title":"Process Optimization for CMOS Compatible MEMS Capacitive Acoustic Sensor","authors":"Ming Li, Xiaoxu Kang, Xiaolan Zhong","doi":"10.1109/ASICON52560.2021.9620398","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620398","url":null,"abstract":"CMOS compatible MEMS capacitive acoustic sensor was designed, developed and optimized on 150mm CMOS Line. Standard LPCVD was used to develop low stress poly film for back-plate and membrane structure. Reflow process was used to solve the problem induced by high step height. Stop structure was used to avoid stiction problem during releasing process. Additional implant process was used to achieve substrate ohmic contact. And after integration process optimization, good physical profile, electrical performance and yield can be obtained which can match the sensor requirements.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"C-32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126488355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Hardware Acceleration of Elliptic-Curve based Crypto-Algorithm, ECDSA and Pairing Engines 基于椭圆曲线的加密算法、ECDSA和配对引擎的硬件加速
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620402
M. Ikeda
{"title":"Hardware Acceleration of Elliptic-Curve based Crypto-Algorithm, ECDSA and Pairing Engines","authors":"M. Ikeda","doi":"10.1109/ASICON52560.2021.9620402","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620402","url":null,"abstract":"We have been working on design of hardware accelerators for various Elliptic-Curve based Crypto-Algorithm, such as ECDSA and Pairing Engines. Here, we present the designs of ECDSA using P-256 Short Weierstrass curve, which has the smallest gate count and the fastest performance ever reported. We also discuss the design of the pairing engine and designed an optimal ate pairing engine on the BN curve over 254-bit primes. In this paper, we demonstrated two designs: a pairing engine with optimized datapath and a pairing processor with a two-layer sequencer for multi-pairing. All these designs were designed and fabricated in 65nm CMOS SOTB process and demonstrated the measured performance.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115046087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A String-in-string-out 256 Bits eFuse Using Full-custom Design in 55nm Process 采用全定制设计的55nm制程串进串出256位熔丝
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620239
Yang Li, Yuejun Zhang, Steve Yang, Shimin Du, Ye Lin
{"title":"A String-in-string-out 256 Bits eFuse Using Full-custom Design in 55nm Process","authors":"Yang Li, Yuejun Zhang, Steve Yang, Shimin Du, Ye Lin","doi":"10.1109/ASICON52560.2021.9620239","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620239","url":null,"abstract":"Electrically programmable fuse (eFuse) is a one-time programmable memory and compatible with CMOS process. eFuse permanently store the key information and adopts parallel structure in large-scale integrated circuits. However, this structure causes area problem with decoder circuit. Therefore, this paper proposes an eFuse scheme without decoder to save area. This work adopts the full customization method and the idea of series connection to design an eFuse circuit with serial data input and serial output. This article finished under 55nm craft, test the stability of its read-write function. In the programming mode, the programming current reaches more than 15mA, which theoretically shows that the fuse is blown. In the reading mode, the reading current is less than 50uA, the leakage current is less than 2uA, the influence on the electric fuse is negligible. The stability meets the requirements.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129512575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Classical Mathematics and Analog/Mixed-Signal IC Design 经典数学和模拟/混合信号IC设计
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620325
Haruo Kobayashi, Xueyan Bai, Yujie Zhao, Shuhei Yamamoto, Dan Yao, Manato Hirai, Jianglin Wei, Shogo Katayama, A. Kuwana
{"title":"Classical Mathematics and Analog/Mixed-Signal IC Design","authors":"Haruo Kobayashi, Xueyan Bai, Yujie Zhao, Shuhei Yamamoto, Dan Yao, Manato Hirai, Jianglin Wei, Shogo Katayama, A. Kuwana","doi":"10.1109/ASICON52560.2021.9620325","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620325","url":null,"abstract":"This paper states that classical mathematics can lead to the smart analog/mixed-signal circuit design, and introduces several research results from the authors’ laboratory that support this statement.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130708016","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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