A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight

To overcome the memory wall problem, in-memory computing (IMC) is proposed to accelerate matrix multiplication. While existing IMC designs encounter problems in scenes where weight updates frequently because of long latency of weight-update or short weight retention time. This paper proposes a semi-floating gate transistor (SFGT) based IMC design to improve the matrix-multiplication with frequently update weights. Simulation results shows that this design achieves access time of 5.32ns (1b IN/8b W) and energy efficiency of 40.14TOPS/W(1b IN/8b W). Besides, a SFGT IMC based solution combing weight-update with refreshing is proposed for matrix-multiplication and weight-update in multiple in multiple out (MIMO), a typical matrix-multiplication intensive scenes with frequently updated weight.