2021 IEEE 14th International Conference on ASIC (ASICON)最新文献_第8页

Design of Wideband Phase Modulator for 2.4~5.25 GHz Digital Polar Transmitter 2.4~5.25 GHz数字极极发射机宽带相位调制器设计

2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620405

Haoliang Zhu, Zhiqun Li, Zhennan Li, Yan Yao

引用次数: 0

Impact of Evaporated AuNP Thickness on Pseudo-MOS and Its Application in Direct MicroRNA-375 Detection 蒸发AuNP厚度对伪mos的影响及其在MicroRNA-375直接检测中的应用

2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620235

Haihua Wang, Song He, K. Xiao, Yu-Long Jiang, Jing Wan

引用次数: 2

Exploiting Dynamic Bit Sparsity in Activation for Deep Neural Network Acceleration 利用激活中的动态比特稀疏性实现深度神经网络加速

2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620448

Yongshuai Sun, Mengyuan Guo, Dacheng Liang, Shan Tang, Naifeng Jing

{"title":"Exploiting Dynamic Bit Sparsity in Activation for Deep Neural Network Acceleration","authors":"Yongshuai Sun, Mengyuan Guo, Dacheng Liang, Shan Tang, Naifeng Jing","doi":"10.1109/ASICON52560.2021.9620448","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620448","url":null,"abstract":"Data sparsity is important in accelerating deep neural networks (DNNs). However, besides the zeroed values, the bit sparsity especially in activations are oftentimes missing in conventional DNN accelerators. In this paper, we present a DNN accelerator to exploit the bit sparsity by dynamically skipping zeroed bits in activations. To this goal, we first substitute the multiply-and-accumulate (MAC) units with more serial shift-and-accumulate units to sustain the computing parallelism. To prevent the low efficiency caused by the random number and positions of the zeroed bits in different activations, we propose activation-grouping, so that the activations in the same group can be computed on non-zero bits in different channels freely, and synchronization is only needed between different groups. We implement the proposed accelerator with 16 process units (PU) and 16 processing elements (PE) in each PU on FPGA built upon VTA (Versatile Tensor Accelerator) which can integrate seamlessly with TVM compilation. We evaluate the efficiency of our design with convolutional layers in resnet18 respectively, which achieves over 3.2x speedup on average compared with VTA design. In terms of the whole network, it can achieve over 2.26x speedup and over 2.0x improvement on area efficiency.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115375058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Implementation of a CRNN-based low-power keyword recognition system on FPGA 基于crnn的低功耗关键字识别系统的FPGA实现

2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620311

Limo Guo, PengXu Lin, Lei Guo, Bo Liu

引用次数: 1

A CMOS Time-of-Flight Image Sensor with High Dynamic Range Digital Pixel 具有高动态范围数字像素的CMOS飞行时间图像传感器

2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620349

Shanzhe Yu, Yacong Zhang, Fei Zhou, Wengao Lu, Shuyu Lei, Zhongjian Chen

引用次数: 1

An 4th-order N-path Bandpass Filter with a Tuning Range of 1-30 GHz and OOB Rejection > 30 dB in 28 nm CMOS 一种4阶n路带通滤波器，调谐范围为1- 30ghz, OOB抑制> 30db

2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620337

Xi Wang, Junyan Ren, Shunli Ma

引用次数: 0

A Streaming Feature Extraction Accelerator using DPCM Image Compression Technique for SLAM Applications 基于DPCM图像压缩技术的SLAM应用流特征提取加速器

2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620342

Zhiyuan Wang, Zhuo Zhang, Haowen Chen

{"title":"A Streaming Feature Extraction Accelerator using DPCM Image Compression Technique for SLAM Applications","authors":"Zhiyuan Wang, Zhuo Zhang, Haowen Chen","doi":"10.1109/ASICON52560.2021.9620342","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620342","url":null,"abstract":"The extraction of feature points plays a significant role in simultaneous localization and mapping (SLAM) applications. However, in the streaming architecture of the feature extraction, sizable row buffers are required to store data, usually occupying a large proportion of the hardware area. To ameliorate this problem, in this paper, we propose a streaming feature extraction architecture with narrower row buffers, combined with the differential pulse-code modulation (DPCM) image compression technique. Meanwhile, we improve the data flow to omit the compressions and decompressions in the critical data path by employing a novel strategy of transposing DPCM decompression and linear operation (TDDLO). Moreover, the calculations are further simplified by introducing an approximate algorithm of the rotation calculation. Consequently, the hardware costs are notably saved, while the impact of DPCM compression on power, latency, and accuracy is mitigated. The experimental results reveal at least a 32% reduction in memory compared with state-of-the-art architectures. Simulated by TSMC 28nm CMOS technology, the proposed architecture can process full-HD (1920×1080) images at 241 fps and consume only 52.7 mW power, while the normalized absolute trajectory error increases slightly by 0.2% on the TUM dataset.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125570478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analytical Global Placement for Heterogenous FPGAs Based on the eDensity Model 基于密度模型的异构fpga全局解析布局

2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620442

Huimin Wang, Xingyu Tong, Runming Shi, Sifei Wang, Jun Yu, Jianli Chen

{"title":"Analytical Global Placement for Heterogenous FPGAs Based on the eDensity Model","authors":"Huimin Wang, Xingyu Tong, Runming Shi, Sifei Wang, Jun Yu, Jianli Chen","doi":"10.1109/ASICON52560.2021.9620442","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620442","url":null,"abstract":"Recent years have seen increased research attention given towards the global placement problem due to the growing capability and heterogeneity of FPGAs. Designed specially for heterogeneous FPGAs, a novel analytical algorithm for global placement problem is proposed and introduced in this paper. On the basis of the eDensity model , our well-proven algorithm aims to get a high-quality solution without efficiency loss. Besides, a fence region processing strategy is implemented to satisfy the heterogeneity constraints. To make the placement solution more compact and thus optimize the total wirelength, we inject appropriate doses of redundant eDensity charges onto instances to be placed. Furthermore, a repulsive force generation technology is adopted to prevent cells from entering the unplaceable regions. We use the nonlinear optimizer to solve our heterogenous objective function. Experimental results on modern industry benchmarks show that our proposed algorithm achieves 8.16% wirelength reduction and 38.89% runtime acceleration on average compared with the commercial tool Procise™.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126159516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Highly Efficient Modulo Loop Pipeline For High Level Synthesis 用于高阶合成的高效模环路管道

2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620276

Chang Wu, Jundong Xie, Kexin Wang

引用次数: 0

A New Sparsity Preserving Model Order Reduction Algorithm for Multi-terminal RC Networks 一种新的多终端RC网络稀疏保持模型降阶算法

2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620477

Xin Chen, Lin Pan, Yangxin Xiang

引用次数: 0