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2021 IEEE 14th International Conference on ASIC (ASICON)最新文献

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A Low Power Real-Time DC Removal Circuit for PPG Readout 一种用于PPG读出的低功耗实时直流去除电路
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620282
Tingting Wei, Qiong Wang, Z. Yuan, Zhiliang Hong
{"title":"A Low Power Real-Time DC Removal Circuit for PPG Readout","authors":"Tingting Wei, Qiong Wang, Z. Yuan, Zhiliang Hong","doi":"10.1109/ASICON52560.2021.9620282","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620282","url":null,"abstract":"A low-power real-time DC removal circuit for PPG readout is proposed. A moving average filter is used to extract real-time DC voltage. Four sampling capacitors are used, three of which are used for storing the sampled input voltages, and the remaining one is used to store the average value. As the circuit continues to cycle, the weight of the older average voltage is getting lower and lower, to achieve the moving average. The removal operation is implemented by a switched capacitor subtractor with a low-power class AB amplifier. The proposed circuit is embedded between the transimpedance amplifier and the quantizer. A multi-phase clock generator is used to generate switch control signals. Implemented in 0.18μm CMOS technology, simulation results show that this DC removal circuit can remove real-time DC offset and suppress slow DC drift. The simulated SNDR improvement of the proposed circuit is 40.5dB. The power consumption of the proposed circuit is 6 μW under the supply voltage of 1.2V.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129051341","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector 基于相位误差检测器的功率波动抗扰度自适应DLL更新方案
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620534
Siman Li, Chris Eom, Jake Jung, Brian Lee, Edwin Kim, Kanyu Cao
{"title":"Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector","authors":"Siman Li, Chris Eom, Jake Jung, Brian Lee, Edwin Kim, Kanyu Cao","doi":"10.1109/ASICON52560.2021.9620534","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620534","url":null,"abstract":"This paper presents an adaptive update scheme for all digital delay locked loop(ADDLL). To reduce the output jitter induced by the power fluctuation, the proposed ADDLL adaptively adjust the variable delay line step using a phase error detector. The phase error detector detects the phase error variation every sixteen external clock period. Once the phase error over the threshold, the adaptive update engine is activated to suppress the power fluctuation. The proposed ADDLL achieve that the tDQSCK (DQS rising edge output timing location from rising edge of CK) drift is under +/-35ps when the power fluctuation is +/-60mV.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129095412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Timing Mismatch Background Calibration Technique with High-Precision Skew Estimation 高精度倾斜估计的时序失配背景校正技术
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620473
Zhifei Lu, X. Peng, Zhaofeng Ren, H. Tang, Bin Guo
{"title":"A Timing Mismatch Background Calibration Technique with High-Precision Skew Estimation","authors":"Zhifei Lu, X. Peng, Zhaofeng Ren, H. Tang, Bin Guo","doi":"10.1109/ASICON52560.2021.9620473","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620473","url":null,"abstract":"This paper presents a novel background calibration technique for timing mismatch in time-interleaved ADCs (TI ADCs). It can achieve high-precision timing mismatch estimation by subtracting the error term caused by noise and jitter in the correlation-based method. Compared to previous works on timing mismatch estimation, this work could achieve higher precision with less samples. Finally, we validate this technique in a 4-cahnnel 12-bit 1GSps TI ADC model with non-ideal effects. Simulation results show that the estimation accuracy of our proposed method could reach 11fs at fin = 2039/ 4096 fs with 210 samples. Furthermore, the technique increases the SNDR and SFDR from 52.72dB and 56.58 dB to 63.27 dB and 87.12 dB, respectively, compared to the techniques using conventional correlation-based estimation.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131285150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Current Research Status and Future Prospect of the In-Memory Computing 内存计算的研究现状与展望
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620412
Shifan Gao, F. Yang, Liang Zhao, Yi Zhao
{"title":"Current Research Status and Future Prospect of the In-Memory Computing","authors":"Shifan Gao, F. Yang, Liang Zhao, Yi Zhao","doi":"10.1109/ASICON52560.2021.9620412","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620412","url":null,"abstract":"Featured with high performance density and energy efficiency, in-memory computing is emerging as an important ASIC formalism for computation-intensive tasks. In this review we will start with an introduction to the in-memory computing architecture, and then move on to discuss its two key enabling technologies, namely massive-capacity embedded memory and massively parallel analog computing, followed by applications and future prospect.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132489283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
CongestNN: An Bi-Directional Congestion Prediction Framework for Large-Scale Heterogeneous FPGAs 面向大规模异构fpga的双向拥塞预测框架
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620520
Chenyue Ma, Yifeng Xiao, Sifei Wang, Jun Yu, Jianli Chen
{"title":"CongestNN: An Bi-Directional Congestion Prediction Framework for Large-Scale Heterogeneous FPGAs","authors":"Chenyue Ma, Yifeng Xiao, Sifei Wang, Jun Yu, Jianli Chen","doi":"10.1109/ASICON52560.2021.9620520","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620520","url":null,"abstract":"As FPGA technology continues scaling, design closure process requires more iterations during placement and routing (P&R) for large designs. Accurate advanced routing congestion prediction can effectively relieve this problem on a large scale, which is considered as one of the most significant and toughest tasks in the FPGA design flow. This paper proposes a novel deep-learning framework named CongestNN to predict routing congestion maps of both horizontal and vertical directions in the global placement (GP) stage with a unique combination of GP-based features. A-net, a newly designed type of Fully Convolutional Network (FCN), is deployed to accomplish the prediction part given the input features. The model is trained and tested on GPU using 22,682 cropped feature maps derived from 112 industrial benchmarks placed by the Procise placer and corresponding golden congestion images supplied by Xilinx Vivado. CongestNN is also incorporated into Procise straightforward to provide instant congestion predictions with the average PCC of 95.18%, while the runtime merely takes over one second.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131973221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A CNN Hardware Accelerator Designed for YOLO Algorithm Based on RISC-V SoC 基于RISC-V SoC的YOLO算法CNN硬件加速器设计
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620500
Xinyu Qin, Xudong Liu, Jun Han
{"title":"A CNN Hardware Accelerator Designed for YOLO Algorithm Based on RISC-V SoC","authors":"Xinyu Qin, Xudong Liu, Jun Han","doi":"10.1109/ASICON52560.2021.9620500","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620500","url":null,"abstract":"YOLO (You Only Look Once) has been widely used in the field of object detection because of its extremely fast real-time calculation speed and good migration ability. In recent years, the design of artificial intelligence systems with high real-time and low energy consumption has become a research hotspot. In this paper, we propose a CNN hardware accelerator specifically designed for YOLOv3-Tiny to increase the calculation parallelism while reducing the frequency of memory access. The design is configured and controlled by T-Head C910, a state-of-art open source multi-core processor based on RISC-V architecture. Experimental results show that the design can provide effective throughput improvement for small embedded systems with limited resources.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134631469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Dual Path Hybrid Step-Up Converter with Enhanced Drive Voltage for Low Voltage Applications 一种用于低压应用的具有增强驱动电压的双路径混合升压变换器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620306
Hailiang Xiong, Bingqing Zhao, Rui Yang, Zeya Xie, Shaowei Zhen, Dongming Ding, Bo Zhang
{"title":"A Dual Path Hybrid Step-Up Converter with Enhanced Drive Voltage for Low Voltage Applications","authors":"Hailiang Xiong, Bingqing Zhao, Rui Yang, Zeya Xie, Shaowei Zhen, Dongming Ding, Bo Zhang","doi":"10.1109/ASICON52560.2021.9620306","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620306","url":null,"abstract":"A novel dual path hybrid step-up (DPSU) converter is proposed in this paper. An inductor and a flying capacitor are adopted as power conversion elements. The proposed converter can produce a higher conversion ratio (CR) with the same duty cycle compared to conventional boost (CB) converter. The voltage stress of power devices is relieved in the DPSU converter and the average inductor current is also reduced leading to lower power loss caused by dc resistance (DCR) of inductor. Furthermore, a negative-voltage switching node is obtained by DPSU converter and a charge-sharing based bootstrap gate driver is designed. The bootstrap gate driver takes use of the negative-voltage switching node, which can enhance driving voltage even at low input voltage. Circuit design is therefore simplified and efficiency is further improved. Simulation results show when input voltage and load current is 2.7V and 1A respectively, the conversion efficiency of DPSU converter is 11.34% higher than that of CB converter.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132998289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 300GHz CMOS Transceiver Targeting 6G 一种针对6G的300GHz CMOS收发器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620250
M. Fujishima
{"title":"A 300GHz CMOS Transceiver Targeting 6G","authors":"M. Fujishima","doi":"10.1109/ASICON52560.2021.9620250","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620250","url":null,"abstract":"A 44 GHz frequency band from 252 GHz to 296 GHz has been identified for telecommunications. This frequency band is a part of the 300 GHz band, which is expected to be utilized for ultra-high speed wireless communication toward 6G. In this talk, an overview of ultra-wideband wireless communication using the 300 GHz band is given and the necessity of a communication system using a phased array is clarified. Finally, a 300 GHz CMOS wireless transceiver, which can be used as an element of this phased array and can transmit data rates of up to 80 Gb/s, is introduced.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133200328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 12-bit 800MS/s pipelined A/D converter 一个12位800MS/s的流水线A/D转换器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620237
Haoran Wang, Fule Li
{"title":"A 12-bit 800MS/s pipelined A/D converter","authors":"Haoran Wang, Fule Li","doi":"10.1109/ASICON52560.2021.9620237","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620237","url":null,"abstract":"Pipelined A/D converter is widely used in high speed applications. In this paper, a 12-bit 800-Msample/s pipelined ADC with a differential input voltage of 1.6Vpp implemented in a 55-nm LL CMOS process is presented. For the purpose of obtaining fine performance with high frequencies input, a SHA with a flip-around structure is employed in the front-end of the pipelined ADC. This design is finished with comprehensive consideration includes speed, parasitic, area, and the distribution in the voltage domain. To shift the different levels of voltage, a level-shift data flip-flop (LSDFF) is used. Under the low-voltage supply of 1.5V, this pipelined ADC achieves about 64.8dB of SNDR with 1496MHz input at 800MS/s.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133475876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process 一种采用28nm CMOS工艺的0.9V电源12.5Gb/s LVDS接收器
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620302
Jinrong Li, Jue Wang, Xu Cheng, Yicheng Zeng, Xiao-Qing Zeng
{"title":"A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process","authors":"Jinrong Li, Jue Wang, Xu Cheng, Yicheng Zeng, Xiao-Qing Zeng","doi":"10.1109/ASICON52560.2021.9620302","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620302","url":null,"abstract":"This paper presents the design of ultra-high-speed low-voltage differential signal (LVDS) I/O interface circuits. A cascaded receiver with common-mode feedback (CMFB) is proposed to achieve the high speed, including a current-reuse pre-amplifier to increase the power efficiency and provide voltage gain at high frequency. The whole design is implemented in a 28 nm CMOS process. The post-layout simulation results show that the power consumption of the transmitter and receiver at 12.5 Gb/s are 10.29 mW and 0.94 mW, respectively. The energy efficiency of the transmitter and receiver at 12.5 Gb/s are 0.82 pJ/bit and 0.08 pJ/bit, respectively.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"577 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123933647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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