Adaptive DLL Update Scheme for Power Fluctuation Immunity Using Phase Error Detector

Abstract

This paper presents an adaptive update scheme for all digital delay locked loop(ADDLL). To reduce the output jitter induced by the power fluctuation, the proposed ADDLL adaptively adjust the variable delay line step using a phase error detector. The phase error detector detects the phase error variation every sixteen external clock period. Once the phase error over the threshold, the adaptive update engine is activated to suppress the power fluctuation. The proposed ADDLL achieve that the tDQSCK (DQS rising edge output timing location from rising edge of CK) drift is under +/-35ps when the power fluctuation is +/-60mV.