A 12-bit 800MS/s pipelined A/D converter

Abstract

Pipelined A/D converter is widely used in high speed applications. In this paper, a 12-bit 800-Msample/s pipelined ADC with a differential input voltage of 1.6Vpp implemented in a 55-nm LL CMOS process is presented. For the purpose of obtaining fine performance with high frequencies input, a SHA with a flip-around structure is employed in the front-end of the pipelined ADC. This design is finished with comprehensive consideration includes speed, parasitic, area, and the distribution in the voltage domain. To shift the different levels of voltage, a level-shift data flip-flop (LSDFF) is used. Under the low-voltage supply of 1.5V, this pipelined ADC achieves about 64.8dB of SNDR with 1496MHz input at 800MS/s.