{"title":"一种采用28nm CMOS工艺的0.9V电源12.5Gb/s LVDS接收器","authors":"Jinrong Li, Jue Wang, Xu Cheng, Yicheng Zeng, Xiao-Qing Zeng","doi":"10.1109/ASICON52560.2021.9620302","DOIUrl":null,"url":null,"abstract":"This paper presents the design of ultra-high-speed low-voltage differential signal (LVDS) I/O interface circuits. A cascaded receiver with common-mode feedback (CMFB) is proposed to achieve the high speed, including a current-reuse pre-amplifier to increase the power efficiency and provide voltage gain at high frequency. The whole design is implemented in a 28 nm CMOS process. The post-layout simulation results show that the power consumption of the transmitter and receiver at 12.5 Gb/s are 10.29 mW and 0.94 mW, respectively. The energy efficiency of the transmitter and receiver at 12.5 Gb/s are 0.82 pJ/bit and 0.08 pJ/bit, respectively.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"577 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process\",\"authors\":\"Jinrong Li, Jue Wang, Xu Cheng, Yicheng Zeng, Xiao-Qing Zeng\",\"doi\":\"10.1109/ASICON52560.2021.9620302\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of ultra-high-speed low-voltage differential signal (LVDS) I/O interface circuits. A cascaded receiver with common-mode feedback (CMFB) is proposed to achieve the high speed, including a current-reuse pre-amplifier to increase the power efficiency and provide voltage gain at high frequency. The whole design is implemented in a 28 nm CMOS process. The post-layout simulation results show that the power consumption of the transmitter and receiver at 12.5 Gb/s are 10.29 mW and 0.94 mW, respectively. The energy efficiency of the transmitter and receiver at 12.5 Gb/s are 0.82 pJ/bit and 0.08 pJ/bit, respectively.\",\"PeriodicalId\":233584,\"journal\":{\"name\":\"2021 IEEE 14th International Conference on ASIC (ASICON)\",\"volume\":\"577 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 14th International Conference on ASIC (ASICON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON52560.2021.9620302\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 14th International Conference on ASIC (ASICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON52560.2021.9620302","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process
This paper presents the design of ultra-high-speed low-voltage differential signal (LVDS) I/O interface circuits. A cascaded receiver with common-mode feedback (CMFB) is proposed to achieve the high speed, including a current-reuse pre-amplifier to increase the power efficiency and provide voltage gain at high frequency. The whole design is implemented in a 28 nm CMOS process. The post-layout simulation results show that the power consumption of the transmitter and receiver at 12.5 Gb/s are 10.29 mW and 0.94 mW, respectively. The energy efficiency of the transmitter and receiver at 12.5 Gb/s are 0.82 pJ/bit and 0.08 pJ/bit, respectively.
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