CongestNN: An Bi-Directional Congestion Prediction Framework for Large-Scale Heterogeneous FPGAs

Abstract

As FPGA technology continues scaling, design closure process requires more iterations during placement and routing (P&R) for large designs. Accurate advanced routing congestion prediction can effectively relieve this problem on a large scale, which is considered as one of the most significant and toughest tasks in the FPGA design flow. This paper proposes a novel deep-learning framework named CongestNN to predict routing congestion maps of both horizontal and vertical directions in the global placement (GP) stage with a unique combination of GP-based features. A-net, a newly designed type of Fully Convolutional Network (FCN), is deployed to accomplish the prediction part given the input features. The model is trained and tested on GPU using 22,682 cropped feature maps derived from 112 industrial benchmarks placed by the Procise placer and corresponding golden congestion images supplied by Xilinx Vivado. CongestNN is also incorporated into Procise straightforward to provide instant congestion predictions with the average PCC of 95.18%, while the runtime merely takes over one second.