A Timing Mismatch Background Calibration Technique with High-Precision Skew Estimation

Abstract

This paper presents a novel background calibration technique for timing mismatch in time-interleaved ADCs (TI ADCs). It can achieve high-precision timing mismatch estimation by subtracting the error term caused by noise and jitter in the correlation-based method. Compared to previous works on timing mismatch estimation, this work could achieve higher precision with less samples. Finally, we validate this technique in a 4-cahnnel 12-bit 1GSps TI ADC model with non-ideal effects. Simulation results show that the estimation accuracy of our proposed method could reach 11fs at fin = 2039/ 4096 fs with 210 samples. Furthermore, the technique increases the SNDR and SFDR from 52.72dB and 56.58 dB to 63.27 dB and 87.12 dB, respectively, compared to the techniques using conventional correlation-based estimation.