A 0.9V Supply 12.5Gb/s LVDS Receiver in 28nm CMOS Process

Abstract

This paper presents the design of ultra-high-speed low-voltage differential signal (LVDS) I/O interface circuits. A cascaded receiver with common-mode feedback (CMFB) is proposed to achieve the high speed, including a current-reuse pre-amplifier to increase the power efficiency and provide voltage gain at high frequency. The whole design is implemented in a 28 nm CMOS process. The post-layout simulation results show that the power consumption of the transmitter and receiver at 12.5 Gb/s are 10.29 mW and 0.94 mW, respectively. The energy efficiency of the transmitter and receiver at 12.5 Gb/s are 0.82 pJ/bit and 0.08 pJ/bit, respectively.