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2021 IEEE 14th International Conference on ASIC (ASICON)最新文献

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A High-Precision Delta Sigma ADC with Chopper in BMS BMS中带斩波的高精度Delta Sigma ADC
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620517
Bo Wang, Wentao Lu, J. Wang, Kai Cheng, F. Fu, F. Lai, Yongsheng Wang
{"title":"A High-Precision Delta Sigma ADC with Chopper in BMS","authors":"Bo Wang, Wentao Lu, J. Wang, Kai Cheng, F. Fu, F. Lai, Yongsheng Wang","doi":"10.1109/ASICON52560.2021.9620517","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620517","url":null,"abstract":"This paper presents a high-precision, low-power Delta Sigma ADC design, using a single-loop fourth-order feedforward modulator structure with an oversampling ratio of 128, which improves the conversion accuracy while reducing the output range of each integrator. A 5-stage CIC filter is used to reduce area and power consumption, and the decimation rate is configurable to achieve different output data rates from 7.8125Hz -1000Hz. The default decimation rate is 256, and the corresponding output data rate is 1000Hz. The amplifier chopping technology and sampling capacitor chopping technology are used to reduce the influence of low-frequency noise and DC offset and improve the overall performance. The ADC is implemented by tsmc 0.18μm CMOS process. According to the chip test results, when the power supply voltage is 5V and the data rate is 1000Hz, the noise of the ADC is 2.23μVRMS, and the data rate is 7.8125Hz, the noise of the ADC is 0.16μVRMS, and the current consumption of the analog modulator circuit is about 220μA.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123423842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research of Scale Recurrent Generative Network on Image Inpainting 尺度递归生成网络在图像绘制中的研究
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620457
Ziyi Zhang, Dong Lyu, Wei Xu
{"title":"Research of Scale Recurrent Generative Network on Image Inpainting","authors":"Ziyi Zhang, Dong Lyu, Wei Xu","doi":"10.1109/ASICON52560.2021.9620457","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620457","url":null,"abstract":"Existing learning-based inpainting methods have recently reached notable success in filling irregular holes. However, the quantity of network parameters in these methods also grows rapidly, thus making them difficult for training and deployment on resource-limited platforms. In this paper, we propose a Scale Recurrent Generative Network (SRGN), in which a new scale recurrent structure is raised and deployed on top of the general learning-based inpainting methods. The scale recurrent procedure stores the context information in different scales to achieve better memorability while keeping the network parameters in the same order of magnitude. To add the iterations on scale dimension, we combine max pooling and average pooling in the downsampling procedure and introduce scale factor in the loss function. The qualitative and quantitative comparisons on the Places2 dataset show that the texture and detail of our generated image are significantly improved in comparison with peer works.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124504913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A process optimization method for carrier stored trench bipolar transistor (CSTBT) device 一种载流子存储槽双极晶体管(CSTBT)器件的工艺优化方法
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620236
Hang Xu, Dong-Hui Zhao, Hao Zhu, Qingqing Sun, David-Wei Zhang
{"title":"A process optimization method for carrier stored trench bipolar transistor (CSTBT) device","authors":"Hang Xu, Dong-Hui Zhao, Hao Zhu, Qingqing Sun, David-Wei Zhang","doi":"10.1109/ASICON52560.2021.9620236","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620236","url":null,"abstract":"This paper presents a process optimization method for the carrier stored trench bipolar transistor (CSTBT) device demonstrated by TCAD numerical simulations. By adjusting the injection sequence of carrier stored (CS) layer, the injection efficiency of the CS layer has been significantly improved, and the trade-off of on-state voltage drop (Von) and collector saturation current (ICsat) has been almost fully optimized. TCAD simulation results show that the ICsat and Von of the CSTBT with optimized process are reduced by 19.7% and 15.1%, respectively. Additionally, comparing the CSTBT with the same Von under the two processes, the ICsat and turn-off time of the CSTBT with optimized process are reduced by 76.1% and 7.8%, respectively. Besides, after the process optimization, the gate trench depth of the device can be further reduced. Result shows shallower gate trench can offer larger design freedom for obtaining excellent trade-off relationship between turn-off loss (Eoff) and Von. Therefore, this process optimization method is an attractive solution for power electronics applications.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124814504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Overview of Design, Fabrication, and Cooling Techniques of 3D-ICs 3d - ic的设计、制造和冷却技术概述
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620436
I. Abdel-Motaleb
{"title":"An Overview of Design, Fabrication, and Cooling Techniques of 3D-ICs","authors":"I. Abdel-Motaleb","doi":"10.1109/ASICON52560.2021.9620436","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620436","url":null,"abstract":"3D-IC technology is the most promising technique to overcome moore’s law failure and deliver the needed integration density for the coming decades. This technology suffers from severe thermal management issues that may result in real reliability issues. These issues require the use of new cooling techniques. In this paper, the different conventional cooling techniques for thermal management are discussed. Liquid cooling using embedded micro-channels are analyzed theoretically and verified experimentally.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125363119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
LSI Testing: A Core Technology to a Successful LSI Industry LSI测试:成功LSI产业的核心技术
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620418
X. Wen
{"title":"LSI Testing: A Core Technology to a Successful LSI Industry","authors":"X. Wen","doi":"10.1109/ASICON52560.2021.9620418","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620418","url":null,"abstract":"Despite its ever-growing importance in all innovation fields, such as automotive and IoT applications, the LSI industry is fragile due to its a weak technology-business chain. In addition, its products, namely LSI chips, are vulnerable to six risks (defective chip escape, radiation, aging, malicious attack, counterfeiting). LSI testing is the technology that is indispensable to mitigate these risks. This paper highlights the intent of LSI testing as well as its impact on the LSI industry.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126213273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 60 GHz Broadband Wearable Antenna for Body-to-Body Communications 用于身体对身体通信的60 GHz宽带可穿戴天线
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620322
Yutong Zhang, Rui Yin, Xiaoliang Shen, N. Yan, G. A. Safdar, M. Rehman
{"title":"A 60 GHz Broadband Wearable Antenna for Body-to-Body Communications","authors":"Yutong Zhang, Rui Yin, Xiaoliang Shen, N. Yan, G. A. Safdar, M. Rehman","doi":"10.1109/ASICON52560.2021.9620322","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620322","url":null,"abstract":"This paper presents a broadband antenna designed on flexible liquid crystal polymer (LCP) substrate for body-to-body short-range communications in 60 GHz frequency band. The antenna provides a wideband characteristic that covers the 51.1-70 GHz band centered at 60 GHz, owing to a coplanar waveguide (CPW) fed slotted patch structure. It attains a gain of 7.4 dBi and efficiency of 98% in the free space while 10.5 dBi and 67% in the on-body configuration. Through simulation and numerical analysis, paired antennas can cover at least 3.9-meter line-of-sight (LOS) body-to-body communications.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129699930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Divide and Conquer: Floating-Point Exponential Calculation Based on Taylor-Series Expansion 分而治之:基于泰勒级数展开的浮点指数计算
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620253
Jianglin Wei, A. Kuwana, Haruo Kobayashi, K. Kubo
{"title":"Divide and Conquer: Floating-Point Exponential Calculation Based on Taylor-Series Expansion","authors":"Jianglin Wei, A. Kuwana, Haruo Kobayashi, K. Kubo","doi":"10.1109/ASICON52560.2021.9620253","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620253","url":null,"abstract":"This paper presents an algorithm to compute the exponential exp(x) floating-point tails based on Taylor- series expansion with mantissa region division. exp(x) is expanded in different regions with corresponding central values using Taylor-series and the best result is selected from among the different convergence ranges obtained. We show the cases of x>0 as well as x<0, and then show the tradeoff among LUT size and the required numbers of additions, subtractions and multiplications, and also computing accuracy of exp(x) by Taylor expansion through simulation results. The designer can choose the best algorithm to build a reasonable hardware system by the method described in this paper.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122024914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Single-Slope PWM Imaging Method for Multi-Mode Dynamic Vision Sensor 多模动态视觉传感器的单斜率PWM成像方法
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620421
Qijuan Wu, Mingyu Wang, Jingjing Liu, Wenhong Li
{"title":"A Single-Slope PWM Imaging Method for Multi-Mode Dynamic Vision Sensor","authors":"Qijuan Wu, Mingyu Wang, Jingjing Liu, Wenhong Li","doi":"10.1109/ASICON52560.2021.9620421","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620421","url":null,"abstract":"To break through the limitation of dynamic vision sensor (DVS) in object recognition and classification, a pulse width modulation (PWM) imaging method in a multi-mode DVS which integrates temporal contrast detection with brightness measurement is proposed. The improved logarithmic photoreceptor with pulse coding strategy ensures a theoretical intra-scene dynamic range of 130 dB. The 128×128 vision sensor has been implemented in a 0.18 µm 2P4M CMOS technology. The pixel pitch is 16.5 µm and the chip occupies a silicon area of 3.9×3.5 mm2. The log sensitivity of our pixel has been verified to be164 mV/Dec in chip testing.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122434594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A LVTSCR-Based Compact Structure for Latch-up Immune 一种基于lvtscr的紧凑型闭锁免疫结构
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620404
Songyan Wang, X. Fan, Zhihua Zhu, Yingtao Zhang, Ruike Chen, J. Liou
{"title":"A LVTSCR-Based Compact Structure for Latch-up Immune","authors":"Songyan Wang, X. Fan, Zhihua Zhu, Yingtao Zhang, Ruike Chen, J. Liou","doi":"10.1109/ASICON52560.2021.9620404","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620404","url":null,"abstract":"In this paper, an improved low-voltage-triggered silicon-controlled rectifier with an embedded shunt path (LVTSCR-ESP) for latch-up immune is proposed. Multi-current pulses are applied to devices, mimicking human body model (HBM) by using Sentaurus-TCAD. The results reveal that the proposed structure, compared with conventional LVTSCR, has adjustable holding voltage, lower trigger voltage and good electrostatic discharge (ESD) robustness. In addition, the working mechanisms are also investigated, and the proposed device as the ESD cell, possessing many advantages, is more benefit for the internal circuit and has no risk of latch-up.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124080934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Enhanced SSCP for Frequency Drift Suppressing in SSPLL 一种用于SSPLL抑制频率漂移的增强SSCP
2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI: 10.1109/ASICON52560.2021.9620261
Chenyue Shi, Shengyuan Zhou, Jing Jin
{"title":"An Enhanced SSCP for Frequency Drift Suppressing in SSPLL","authors":"Chenyue Shi, Shengyuan Zhou, Jing Jin","doi":"10.1109/ASICON52560.2021.9620261","DOIUrl":"https://doi.org/10.1109/ASICON52560.2021.9620261","url":null,"abstract":"An enhanced Sub-Sampling Charge Pump (SSCP) for suppressing the frequency drift of Sub-sampling Phase-Locked Loop (SSPLL) is proposed. The enhanced SSCP consists an input stage, the current mirrors, and an output stage for selecting the effective period, which is highlighted in this paper. The function of the SSCP is to convert the voltage sampled by the Sub-Sampling Phase Detector (SSPD) into current signal and then charge the Loop Filter (LF). Unlike the traditional SSCP, whose output stage is a simple switch array, the proposed SSCP output stage includes a capacitor and customized switches. By charging the capacitor and then charging the LF by the capacitor, the deviation of the output voltage existed at the rising edge of the reference clock is eliminated, thus the frequency drift is suppressed. To verify the advantages of the proposed SSCP, a complete Phase-Locked Loop (PLL) based on 180nm process was built. The simulated phase noise of the SSPD and the SSCP is -201dBc/Hz@1MHz.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126718049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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