A High-Precision Delta Sigma ADC with Chopper in BMS

Abstract

This paper presents a high-precision, low-power Delta Sigma ADC design, using a single-loop fourth-order feedforward modulator structure with an oversampling ratio of 128, which improves the conversion accuracy while reducing the output range of each integrator. A 5-stage CIC filter is used to reduce area and power consumption, and the decimation rate is configurable to achieve different output data rates from 7.8125Hz -1000Hz. The default decimation rate is 256, and the corresponding output data rate is 1000Hz. The amplifier chopping technology and sampling capacitor chopping technology are used to reduce the influence of low-frequency noise and DC offset and improve the overall performance. The ADC is implemented by tsmc 0.18μm CMOS process. According to the chip test results, when the power supply voltage is 5V and the data rate is 1000Hz, the noise of the ADC is 2.23μVRMS, and the data rate is 7.8125Hz, the noise of the ADC is 0.16μVRMS, and the current consumption of the analog modulator circuit is about 220μA.