A process optimization method for carrier stored trench bipolar transistor (CSTBT) device

2021 IEEE 14th International Conference on ASIC (ASICON) Pub Date : 2021-10-26 DOI:10.1109/ASICON52560.2021.9620236

Hang Xu, Dong-Hui Zhao, Hao Zhu, Qingqing Sun, David-Wei Zhang

{"title":"A process optimization method for carrier stored trench bipolar transistor (CSTBT) device","authors":"Hang Xu, Dong-Hui Zhao, Hao Zhu, Qingqing Sun, David-Wei Zhang","doi":"10.1109/ASICON52560.2021.9620236","DOIUrl":null,"url":null,"abstract":"This paper presents a process optimization method for the carrier stored trench bipolar transistor (CSTBT) device demonstrated by TCAD numerical simulations. By adjusting the injection sequence of carrier stored (CS) layer, the injection efficiency of the CS layer has been significantly improved, and the trade-off of on-state voltage drop (Von) and collector saturation current (ICsat) has been almost fully optimized. TCAD simulation results show that the ICsat and Von of the CSTBT with optimized process are reduced by 19.7% and 15.1%, respectively. Additionally, comparing the CSTBT with the same Von under the two processes, the ICsat and turn-off time of the CSTBT with optimized process are reduced by 76.1% and 7.8%, respectively. Besides, after the process optimization, the gate trench depth of the device can be further reduced. Result shows shallower gate trench can offer larger design freedom for obtaining excellent trade-off relationship between turn-off loss (Eoff) and Von. Therefore, this process optimization method is an attractive solution for power electronics applications.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 14th International Conference on ASIC (ASICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON52560.2021.9620236","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

Abstract

This paper presents a process optimization method for the carrier stored trench bipolar transistor (CSTBT) device demonstrated by TCAD numerical simulations. By adjusting the injection sequence of carrier stored (CS) layer, the injection efficiency of the CS layer has been significantly improved, and the trade-off of on-state voltage drop (Von) and collector saturation current (ICsat) has been almost fully optimized. TCAD simulation results show that the ICsat and Von of the CSTBT with optimized process are reduced by 19.7% and 15.1%, respectively. Additionally, comparing the CSTBT with the same Von under the two processes, the ICsat and turn-off time of the CSTBT with optimized process are reduced by 76.1% and 7.8%, respectively. Besides, after the process optimization, the gate trench depth of the device can be further reduced. Result shows shallower gate trench can offer larger design freedom for obtaining excellent trade-off relationship between turn-off loss (Eoff) and Von. Therefore, this process optimization method is an attractive solution for power electronics applications.

查看原文本刊更多论文

一种载流子存储槽双极晶体管(CSTBT)器件的工艺优化方法

本文提出了一种载流子存储沟槽双极晶体管(CSTBT)器件的工艺优化方法，并通过TCAD数值模拟进行了验证。通过调整载流子存储层(CS)的注入顺序，显著提高了CS层的注入效率，并几乎完全优化了导通压降(Von)和集电极饱和电流(ICsat)的权衡。TCAD仿真结果表明，优化后的CSTBT的ICsat和Von分别降低了19.7%和15.1%。另外，两种工艺下的CSTBT与相同Von相比，优化后的CSTBT的ICsat和关断时间分别降低了76.1%和7.8%。此外，经过工艺优化后，该装置的栅沟深度可以进一步减小。结果表明，较浅的栅极沟槽可以提供更大的设计自由度，从而获得良好的关断损耗(Eoff)与Von之间的权衡关系。因此，这种工艺优化方法是电力电子应用的一个有吸引力的解决方案。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2021 IEEE 14th International Conference on ASIC (ASICON)

自引率

0.00%

发文量