A New Sparsity Preserving Model Order Reduction Algorithm for Multi-terminal RC Networks

Abstract

VLSI post-layout parasitic analysis demands more in fast simulation methods of huge and multi-terminal networks. Model order reduction (MOR) can settle for it by smaller model with approximating response at terminals, but destruction of system sparsity can slow down simulation speed a lot. To preserve sparsity, we introduce incomplete LU decomposition and pre-processing procedure into projection-based reduction methods. Experimental results show that the circuit simulation speed improves about 3X-11X with RMS error lower than 2e-3.