Highly Efficient Modulo Loop Pipeline For High Level Synthesis

Abstract

State-of-the-art loop pipeline algorithms use iterative SDC scheduling to compute a best Initiation Interval (II). However, the time complexity of SDC scheduling itself is O(n2(m + nlogn)logn) for a Control and Data Flow Graph (CDFG) with n nodes and m constraints. This can be very high for large loops. In this paper, we propose a linear time scheduling algorithm for loop pipeline without back-tracking. Our test results show that our algorithm can be over 1000x faster than the iterative SDC-based algorithm in LegUp, while achieving the same II. When compared with the industrial tool VivadoHLS, our algorithm can still be over 500x faster, on average, with comparable quality of results.