A 5-156.25Gb/s high pin efficiency Receiver Based on CNRZ-5 for USR High-Speed Interface

Abstract

In order to improve the pin efficiency of the Die to Die (D2D)[1] interface, a CNRZ-5 coding based high speed receiver is proposed in this paper. To improve the signal quality of the receiver at high speed, a multi-input-comparator with equalization is introduced. In addition, a Forward Clock (FCK) structure with first-order data and clock recovery is used to reduce the power of the receiver. This D2D receiver is designed with 28nm CMOS process, and its power supply is 0.9 voltage. The simulation results show that, the receiver can work on 5-156.25Gb/s under a channel with maximum 7.5dB insertion loss at 156.25Gb/s. Furthermore, the receiver pin efficiency can be improved by 66.7% compared with other traditional differential signal receiver.