Hardware Acceleration of Elliptic-Curve based Crypto-Algorithm, ECDSA and Pairing Engines

Abstract

We have been working on design of hardware accelerators for various Elliptic-Curve based Crypto-Algorithm, such as ECDSA and Pairing Engines. Here, we present the designs of ECDSA using P-256 Short Weierstrass curve, which has the smallest gate count and the fastest performance ever reported. We also discuss the design of the pairing engine and designed an optimal ate pairing engine on the BN curve over 254-bit primes. In this paper, we demonstrated two designs: a pairing engine with optimized datapath and a pairing processor with a two-layer sequencer for multi-pairing. All these designs were designed and fabricated in 65nm CMOS SOTB process and demonstrated the measured performance.