A ReRAM-based 10T2R SRAM Using Power-off Recovery Function for Reducing Power

Abstract

To solve the problem of power-off information loss of SRAM, non-volatile circuits are attracting more and more attention. However, there are some problems in the non-volatile circuit, such as long storage time and high-power consumption. In this paper, a scheme of 10T2R non-volatile SRAM use ReRAM is proposed. The 8T SRAM is selected for the high static noise margin (SNM). The addition of ReRAM provides the device with the ability to keep data after power-off and recover data after power-on. Then, the 2T2R structure of non-volatile memory uses a Memristive Voltage Divider (MVD) arrangement, not only saves the circuit area but also reduces the write energy. Finally, the functionality and performance of the ReRAM-based 10T2R SRAM are validated and evaluated in 65nm CMOS technology. The experimental results show that the non-volatile SRAM circuit has the power-off recovery function, and the restore latency needs 9ns. The restore yield of proposed circuit all achieve 100% when ReRAM R-ratio =10 and 20.