A Self-regulating Dynamic Reference Sensing Scheme with Balanced Trade-Off between Read Disturbance and Sensing Margin

Abstract

Spin transfer torque MRAM (STT-MRAM) is a promising candidate for next-generation memory thanks to its high endurance and non-volatility. In low-power scenario, MRAM sensing margin is degraded due to the limited reading current, which makes read operation difficult. This paper proposes a novel self-regulating dynamic reference (SRDR) sensing scheme to alleviate sensing bit-error rate (BER). The proposed scheme optimizes the conventional dynamic reference generator so that the gain and bias of the attenuator can be adaptively changed according to the bit-line voltage. The proposed scheme is evaluated with 65-nm CMOS. Simulation results show significant improvement. Compared with the previous dynamic dual-reference sensing scheme, the proposed scheme improves the sensing margin by 103% at a lower read current (10.09μA, only 18% of the critical switching current) and reduces the BER from 3.5E-02 to 9.6E-06.