Adaptive OCD and ODT Control for Channel S/I Enhancement in DDR4 SDRAM

This paper presents a new method to enhance DRAM memory interface performance. To achieve bigger eye diagram during read and write operation, output driver’s impedance is needed to be controlled respectively. For example, the low output driver’s impedance makes bigger eye during read operation, but the high output driver’s impedance makes bigger eye during write operation. To solve this problem, adaptive OCD and ODT control scheme is presented in this paper. Adopting the adder and subtracter in front of pre-driver inside each DQ block and controlled by read or write command flag, output driver’s impedance can be controlled, during read and write operation, respectively. The proposed scheme enhances 20% voltage margin and 10% timing margin during read operation and 20% voltage margin and 15% timing margin during write operation.