Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch

Abstract

Flip flops/Pulsed latches are one of the main contributors of dynamic power consumption in processors. In this paper, a novel Ultra-low-voltage Low-power Self-adaptive Static Pulsed Latch, SSPL, is proposed. In terms of power consumption, SSPL outperforms prior state-of-the-art pulsed latch up to 60.1% at 10% data switching activity using 1V in a 45nm technology.