{"title":"10bit 1.6GS/s电流导向DAC, 40nm CMOS","authors":"Yukun Zhang, Xinpeng Xing","doi":"10.1109/ASICON52560.2021.9620411","DOIUrl":null,"url":null,"abstract":"In this paper, systematic design of a 10bit 1.6GS/s current-steering (CS) digital-to-analog converter (DAC) is presented. Both two-stage decoder and three latch stages are applied to synchronize input data. To guarantee matching, all bits are implemented by parallel or series of unit current cells; double centroid floorplan and balanced-ring switching are adopted in the layout design. Post-simulation results in 40nm CMOS show that for an input signal up to 550MHz, the SFDR and the SNR of the presented 1.6GS/s DAC achieve 67dB and 61dB respectively, with a maximum output current of 20mA. The DAC consumes 54mW power, from 1.1/2.2V supplies, and occupies 0.072mm2 core area.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 10bit 1.6GS/s Current-steering DAC in 40nm CMOS\",\"authors\":\"Yukun Zhang, Xinpeng Xing\",\"doi\":\"10.1109/ASICON52560.2021.9620411\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, systematic design of a 10bit 1.6GS/s current-steering (CS) digital-to-analog converter (DAC) is presented. Both two-stage decoder and three latch stages are applied to synchronize input data. To guarantee matching, all bits are implemented by parallel or series of unit current cells; double centroid floorplan and balanced-ring switching are adopted in the layout design. Post-simulation results in 40nm CMOS show that for an input signal up to 550MHz, the SFDR and the SNR of the presented 1.6GS/s DAC achieve 67dB and 61dB respectively, with a maximum output current of 20mA. The DAC consumes 54mW power, from 1.1/2.2V supplies, and occupies 0.072mm2 core area.\",\"PeriodicalId\":233584,\"journal\":{\"name\":\"2021 IEEE 14th International Conference on ASIC (ASICON)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE 14th International Conference on ASIC (ASICON)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASICON52560.2021.9620411\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 14th International Conference on ASIC (ASICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON52560.2021.9620411","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, systematic design of a 10bit 1.6GS/s current-steering (CS) digital-to-analog converter (DAC) is presented. Both two-stage decoder and three latch stages are applied to synchronize input data. To guarantee matching, all bits are implemented by parallel or series of unit current cells; double centroid floorplan and balanced-ring switching are adopted in the layout design. Post-simulation results in 40nm CMOS show that for an input signal up to 550MHz, the SFDR and the SNR of the presented 1.6GS/s DAC achieve 67dB and 61dB respectively, with a maximum output current of 20mA. The DAC consumes 54mW power, from 1.1/2.2V supplies, and occupies 0.072mm2 core area.
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