A Three-Stage Comparator with High Speed and Low Power

Abstract

A three-stage comparator with two dynamic pre-amplifiers and a regenerative latch is proposed. The highlight of the proposed comparator is that a positive feedback pre-amplifier is added to the conventional two-stage comparator for higher gain and faster regenerative speed, which greatly suppresses the input-referred noise. In addition, the proposed comparator has almost no current flowing from the power supply to the ground, so it has extraordinary energy efficiency. Implemented in the 28-nm CMOS technology, the proposed comparator achieves a delay of 35.48 ps against 43.3 ps for the traditional comparator with a 25% reduction in power consumption. The resolution of the proposed comparator can be increased to 1 μV and the input-referred noise is reduced by 34% at a clock frequency of 10 GHz.