A 65nm Reliable Near-Subthreshold Standard Cells Design Using Schmitt Trigger

Abstract

The researches of Near-threshold circuits pay much attention to performance and power consumption reduction. With the reduction of power supply voltage, the performance of standard cell circuits provided by foundries is susceptible to noise and process deviations. After researching low-power technology and Schmitt Trigger, we propose a semi-stacked standard cell circuit with high robustness. In order to optimize the logic gate, reduce the leakage current and improve the switch current ratio, we add a feedback transistor at the stack node of the circuit via the hysteresis effect and feedback mechanism of Schmitt Trigger. Then, we utilize the minimum width design method to improve the switching threshold and the driving current of the transistor. Our approach achieves the design of standard cell circuit under the TSMC 65nm CMOS process. The experimental results suggest that compared with previous works, our approach has the smallest coefficient of variance and the noise margin is improved about 11.5%-15.3%.