Ziwei Li, Yutong Zhao, Guoting Wu, Fan Ye, Junyan Ren
{"title":"A Wide-Range 12b 150MS/s P-SAR ADC with Open-Loop Residue Amplifier for Ultrasound AFE","authors":"Ziwei Li, Yutong Zhao, Guoting Wu, Fan Ye, Junyan Ren","doi":"10.1109/ASICON52560.2021.9620280","DOIUrl":null,"url":null,"abstract":"A wide-range wide-band ADC is a crucial part of the high-frequency ultrasound imaging system analog front-end (AFE). This paper presents a wide input range 12b 150MS/s pipelined-SAR ADC design using a novel linearized open-loop subthreshold residue amplifier. The nonlinearity of the traditional subthreshold differential input pair is examined. Based on the examination, a new open-loop amplifier with a combined fully- and pseudo-differential input pair is proposed and mathematically analyzed. The proposed 12b 150MS/s pipelined-SAR ADC with the new residue amplifier is implemented and simulated using 28nm CMOS technology, attaining 74dB SFDR, 63dB SNDR and 14fJ/conv-step with a 1.44V full-scale range.","PeriodicalId":233584,"journal":{"name":"2021 IEEE 14th International Conference on ASIC (ASICON)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE 14th International Conference on ASIC (ASICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASICON52560.2021.9620280","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A wide-range wide-band ADC is a crucial part of the high-frequency ultrasound imaging system analog front-end (AFE). This paper presents a wide input range 12b 150MS/s pipelined-SAR ADC design using a novel linearized open-loop subthreshold residue amplifier. The nonlinearity of the traditional subthreshold differential input pair is examined. Based on the examination, a new open-loop amplifier with a combined fully- and pseudo-differential input pair is proposed and mathematically analyzed. The proposed 12b 150MS/s pipelined-SAR ADC with the new residue amplifier is implemented and simulated using 28nm CMOS technology, attaining 74dB SFDR, 63dB SNDR and 14fJ/conv-step with a 1.44V full-scale range.