A 10bit 1.6GS/s Current-steering DAC in 40nm CMOS

Abstract

In this paper, systematic design of a 10bit 1.6GS/s current-steering (CS) digital-to-analog converter (DAC) is presented. Both two-stage decoder and three latch stages are applied to synchronize input data. To guarantee matching, all bits are implemented by parallel or series of unit current cells; double centroid floorplan and balanced-ring switching are adopted in the layout design. Post-simulation results in 40nm CMOS show that for an input signal up to 550MHz, the SFDR and the SNR of the presented 1.6GS/s DAC achieve 67dB and 61dB respectively, with a maximum output current of 20mA. The DAC consumes 54mW power, from 1.1/2.2V supplies, and occupies 0.072mm2 core area.