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Electrical Performance of Electronic Packaging最新文献

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The importance of inductance and inductive coupling for on-chip wiring 电感和电感耦合对片上布线的重要性
Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634037
Alina Deutsch, Howard H. Smith, G. Katopis, Wiren D. Becker, P. Coteus, C. Surovic, G. Kopcsay, Barry J. Rubin, R. P. Dunne, T. Gallo, D. R. Knebel, B. L. Krauter, L. M. Terman, G. Sai-Halasz, P. J. Reslte
{"title":"The importance of inductance and inductive coupling for on-chip wiring","authors":"Alina Deutsch, Howard H. Smith, G. Katopis, Wiren D. Becker, P. Coteus, C. Surovic, G. Kopcsay, Barry J. Rubin, R. P. Dunne, T. Gallo, D. R. Knebel, B. L. Krauter, L. M. Terman, G. Sai-Halasz, P. J. Reslte","doi":"10.1109/EPEP.1997.634037","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634037","url":null,"abstract":"The importance of inductance and inductive coupling for accurate delay and crosstalk prediction in on-chip interconnections is investigated experimentally for the top three layers in a five-layer wiring structure and guidelines are formulated. In-plane and between-plane crosstalk and delay dependence on driver and receiver circuit device sizes and line lengths and width are analyzed with representative CMOS circuits. Simplified constant-parameter, distributed coupled-line RLC-circuit representation that approximates the waveforms predicted with frequency-dependent line parameters is shown to be feasible.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127116335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
Standardizable and automated procedures to measure and simulate very complex 3D packaging parasitics with highest accuracy, shown for a TSOP50 as example 标准化和自动化的程序，以最高的精度测量和模拟非常复杂的3D封装寄生，以TSOP50为例
Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634067
E. Miersch, S. Muff, M. Jin
{"title":"Standardizable and automated procedures to measure and simulate very complex 3D packaging parasitics with highest accuracy, shown for a TSOP50 as example","authors":"E. Miersch, S. Muff, M. Jin","doi":"10.1109/EPEP.1997.634067","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634067","url":null,"abstract":"The recent development of computing speeds for u-processors and memory, reaching cycle times which correspond to data transfer rates between 400 Mbits/(sec*pin) to 1 GHz/(sec*pin), requires precise and automated procedures, allowing to simulate the complex packaging parasitics of complete packages with experimental accuracy. With the used TSOP50 example it is demonstrated, how the needed automated simulation procedures can be implemented. The simulated results were verified by standardizable experimental procedures. The methodology is capable of describing complete PCBs including the components with layout precision.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131409994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel broadband flip chip interconnection 一种新型宽带倒装芯片互连
Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634070
J. Kim, D. Koh, T. Itoh
{"title":"A novel broadband flip chip interconnection","authors":"J. Kim, D. Koh, T. Itoh","doi":"10.1109/EPEP.1997.634070","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634070","url":null,"abstract":"Flip chip interconnections with CPW structures are studied. A novel broadband flip chip interconnection design is proposed based on the results of the sensitivity analysis performed by the Finite Difference Time Domain (FDTD) method.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129522244","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Buried double bondwires for microwave hermetic packages 微波密封包装用埋地双键线
Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634072
Sung-Jin Kim, Hai-Young Lee
{"title":"Buried double bondwires for microwave hermetic packages","authors":"Sung-Jin Kim, Hai-Young Lee","doi":"10.1109/EPEP.1997.634072","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634072","url":null,"abstract":"Double bondwires buried in a dielectric material is proposed for high frequency hermetic packages and characterized experimentally and theoretically up to 30 GHz. These buried bondwires made it possible to achieve 15 dB improvement of return loss at 20 GHz compared to conventional bondwires.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129247741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measurement and field simulation based characterization of plastic IC packages 基于塑料IC封装特性的测量和现场仿真
Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634066
F. Mernyei
{"title":"Measurement and field simulation based characterization of plastic IC packages","authors":"F. Mernyei","doi":"10.1109/EPEP.1997.634066","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634066","url":null,"abstract":"A method to obtain electrical models for IC packages is introduced. We used measured S-parameters to extract equivalent circuits for the package and surrounding components. The resulted equivalent circuit was verified with 3D field simulation.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116389317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A simultaneous switching noise analysis of a high speed memory module including the test environments and system-level models 高速存储器模块同时开关噪声分析，包括测试环境和系统级模型
Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634050
Joon-Ho Choi, Kyung-Hwa Kim, Jung-Bae Lee, Taek-Soo Kim, J. Kong, Sang-Hoon Lee
{"title":"A simultaneous switching noise analysis of a high speed memory module including the test environments and system-level models","authors":"Joon-Ho Choi, Kyung-Hwa Kim, Jung-Bae Lee, Taek-Soo Kim, J. Kong, Sang-Hoon Lee","doi":"10.1109/EPEP.1997.634050","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634050","url":null,"abstract":"As memory module products become more byte-wide and operate at higher speeds, more of the simultaneous switching noise (SSN) is observed. This paper presents SSN analysis results of high speed memory modules considering the power/ground planes and various interconnects of a test environment and computer system. Using the proposed model, highly accurate simulation results are obtained. Furthermore, we analyze the effect of SSN on the clock jitter and RAS Vil margin. The same model is also used to observe the effect of the decoupling capacitors on SSN. Based on our analysis, memory modules can be redesigned to increase the reliability.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122716527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Importance of damping and resonance in thin-film integrated decoupling capacitor design 阻尼和谐振在薄膜集成去耦电容器设计中的重要性
Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634031
J. Bandyopadhyay, P. Chahal, M. Swaminathan
{"title":"Importance of damping and resonance in thin-film integrated decoupling capacitor design","authors":"J. Bandyopadhyay, P. Chahal, M. Swaminathan","doi":"10.1109/EPEP.1997.634031","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634031","url":null,"abstract":"This paper discusses the design of integrated decoupling capacitors required to suppress delta-I noise in high performance digital packages. The use of damping to reduce the effect of resonance in capacitors is discussed using lossy, gridded structures.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122995400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Special types of coplanar transmission lines suitable up to MM-wave bands 特殊类型的共面传输线，适用于毫米波段
Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634048
J. Svac̆ina
{"title":"Special types of coplanar transmission lines suitable up to MM-wave bands","authors":"J. Svac̆ina","doi":"10.1109/EPEP.1997.634048","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634048","url":null,"abstract":"This paper contains an investigation of two special types of coplanar transmission lines: an asymmetric micro-coplanar line and a new configuration of coplanar line with additional semi-infinite upper ground planes. The conformal mapping method is used to obtain closed-form expressions for basic parameters of both lines. The dispersion and attenuation characteristics are investigated using semi-empirical analysis up to THz frequency bands.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126233400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Utilization of fast algorithm to analyze embedded passive components using commercial EM solvers 利用商业EM求解器快速算法分析嵌入式无源元件
Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634080
K. Choi, M. Swaminathan
{"title":"Utilization of fast algorithm to analyze embedded passive components using commercial EM solvers","authors":"K. Choi, M. Swaminathan","doi":"10.1109/EPEP.1997.634080","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634080","url":null,"abstract":"This paper discusses the analysis of embedded passive components using a rational polynomial approximation. The method combines the accuracy of full wave EM solvers with Cauchy's method to generate the interpolated response using a minimum number of frequency points. It is shown that the method is able to extract the resonance behaviors and quality factor (Q) of embedded passive components with minimum error.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"2677 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125539374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Effect of floating conductive plane on effective inductance 浮动导电平面对有效电感的影响
Electrical Performance of Electronic Packaging Pub Date : 1997-10-27 DOI: 10.1109/EPEP.1997.634051
J. Prince, M. Lopez
{"title":"Effect of floating conductive plane on effective inductance","authors":"J. Prince, M. Lopez","doi":"10.1109/EPEP.1997.634051","DOIUrl":"https://doi.org/10.1109/EPEP.1997.634051","url":null,"abstract":"The effect of a floating metallic plane on the effective inductance for simultaneously switching output (SSO) noise is shown and explained for two different technologies, multilayer and coplanar. The SSO noise advantage of the coplanar geometry with floating plane effects is shown.","PeriodicalId":220951,"journal":{"name":"Electrical Performance of Electronic Packaging","volume":"230 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124543461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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