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2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)最新文献

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VHDL design validation by genetic manipulation techniques 通过基因操作技术验证VHDL设计
2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI: 10.1109/ICMEL.2000.838795
Z. Stamenkovic, H.-Ch. Dahmen, U. Glaeser
{"title":"VHDL design validation by genetic manipulation techniques","authors":"Z. Stamenkovic, H.-Ch. Dahmen, U. Glaeser","doi":"10.1109/ICMEL.2000.838795","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838795","url":null,"abstract":"Formal verification is an important area in industry that gets more and more attention. The growing complexity of digital circuits and its use in safety critical systems are the reasons for the need of tools for checking the correctness of designs. In this paper we present a new approach of model evaluation. With our approach we are able to increase the belief of a designer in the right functionality of a circuit without the long runtimes of classical model checking but with more reliability than testing a design via simulation with few input patterns. To achieve this goal we use our genetic manipulation technique: a combination of classical genetic algorithms with a goal oriented mutation operator, based on a backtracking method.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130713313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A simple model for the threshold voltage of polysilicon TFT which include both grain and grain boundary trapping states 一个包含晶界和晶界捕获态的多晶硅TFT阈值电压的简单模型
2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI: 10.1109/ICMEL.2000.840562
D. Petković
{"title":"A simple model for the threshold voltage of polysilicon TFT which include both grain and grain boundary trapping states","authors":"D. Petković","doi":"10.1109/ICMEL.2000.840562","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.840562","url":null,"abstract":"In this paper, a simple procedure for approximate evaluation of threshold voltage of polysilicon TFT is reported. This procedure takes into account the effect of total depletion of polycrystalline grains. Also, the presented model includes both grain and grain boundary trapping states, and assumes different distributions of these states in the energy gap. Calculations of threshold voltage dependencies on grain size, dopant concentration, and temperature have been reported and discussed.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130424420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Transient analysis of BJT using all injection level TLEC model 采用全注射级TLEC模型对BJT进行瞬态分析
2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI: 10.1109/ICMEL.2000.840543
T.V. Pesic, T. Ilic, N. Jankovic, J. Karamarković
{"title":"Transient analysis of BJT using all injection level TLEC model","authors":"T.V. Pesic, T. Ilic, N. Jankovic, J. Karamarković","doi":"10.1109/ICMEL.2000.840543","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.840543","url":null,"abstract":"Transmission line equivalent circuit model of bipolar junction transistor has been generalized to include all injection level case and model Kirk effect. The obtained model has been used for simulation of time domain transient analysis.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"178 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126355433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Mapping matrix multiplication algorithm onto optimal fault-tolerant systolic array 矩阵乘法算法到最优容错收缩数组的映射
2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI: 10.1109/ICMEL.2000.838789
I. Milovanovic, T. Tokic, M. Stojcev, E. Milovanovic, N. Novakovic
{"title":"Mapping matrix multiplication algorithm onto optimal fault-tolerant systolic array","authors":"I. Milovanovic, T. Tokic, M. Stojcev, E. Milovanovic, N. Novakovic","doi":"10.1109/ICMEL.2000.838789","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838789","url":null,"abstract":"An approach to the design of fault-tolerant hexagonal systolic array (SA) for matrix multiplication is described. The approach comprises of three steps. First, redundancies are introduced at the computational level by deriving three equivalent algorithms but with disjoint index spaces. Second, we perform the accommodation of index spaces to the projection direction to obtain a hexagonal SA with an optimal number of processing elements (PE) for a given problem size. Finally, we perform mapping of the accommodated index spaces using a valid transformation matrix. As a result we obtain an SA with an optimal number of PEs which perform fault-tolerant matrix multiplication. In the case of square matrices of order N/spl times/N this array comprises N/sup 2/+2N PEs.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"4 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113959920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Computationally efficient parametric yield estimation of linear electronic circuits 线性电路的高效参数良率估计
2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI: 10.1109/ICMEL.2000.838781
T. Ilic, V.B. Lirovski
{"title":"Computationally efficient parametric yield estimation of linear electronic circuits","authors":"T. Ilic, V.B. Lirovski","doi":"10.1109/ICMEL.2000.838781","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838781","url":null,"abstract":"This paper recommends a new efficient method for statistical analysis of linear electronic circuits, when elements tolerances are given. The method copes with small and large tolerance values equally. Only one LU factorization of system matrix as whole is necessary, for each frequency/time point. Tolerance simulator was developed on the bases of this method, including graphical postprocessor suitable for observing statistical characteristics, and yield of a circuit.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121367064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Molecular layer epitaxy for future devices 未来器件的分子层外延
2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI: 10.1109/ICMEL.2000.840563
T. Kurabayashi, J. Nishizawa
{"title":"Molecular layer epitaxy for future devices","authors":"T. Kurabayashi, J. Nishizawa","doi":"10.1109/ICMEL.2000.840563","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.840563","url":null,"abstract":"Molecular layer epitaxies (MLE) of GaAs related compounds and Si with SiO/sub 2/ deposition has been developed to realize THz operating devices. At a lower process temperature than for conventional growth methods, device quality epitaxial layers were achieved by molecular layer epitaxy, In GaAs MLE, 100 /spl Aring/ scale static induction transistors are fabricated by MLE operating in a mixed ballistic-tunneling mode or in the pure tunneling mode. For device applications basic research in the fields of surface science and material science are studied.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122704101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Influence of gate oxide charge density on VDMOS transistor ON-resistance 栅极氧化物电荷密度对VDMOS晶体管导通电阻的影响
2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI: 10.1109/ICMEL.2000.838777
Z. Pavlović, I. Manic, Z. Prijić, V. Davidovic, N. Stojadinovic
{"title":"Influence of gate oxide charge density on VDMOS transistor ON-resistance","authors":"Z. Pavlović, I. Manic, Z. Prijić, V. Davidovic, N. Stojadinovic","doi":"10.1109/ICMEL.2000.838777","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838777","url":null,"abstract":"In this paper the influence of net density of gate oxide charge on low-voltage power VDMOS transistor ON-resistance is analyzed. By affecting the threshold voltage, flat-band voltage, and carrier mobilities in channel and accumulation layer regions, variations of gate oxide charge density affect the channel resistance, accumulation layer resistance, and the overall ON-resistance as well. The variation of gate oxide charge density from 10/sup 10/ cm/sup -2/ to 10/sup 11/ cm/sup -2/ causes the ON-resistance to increase for more than 20%.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122774330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design of high-speed gates based on heterostructural technology 基于异质结构技术的高速栅极设计
2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI: 10.1109/ICMEL.2000.838794
Z. Tchakhnakia, I. Sikmashvili, G. D. Didebashvili, R. Melkadze
{"title":"Design of high-speed gates based on heterostructural technology","authors":"Z. Tchakhnakia, I. Sikmashvili, G. D. Didebashvili, R. Melkadze","doi":"10.1109/ICMEL.2000.838794","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838794","url":null,"abstract":"The design technique of digital integrated circuits on BFL gates is represented on the basis of an AlGaAs/GaAs heterostructure. The high electron mobility transistor (HEMT) is simulated and the basic architecture and electrophysical parameters of the heterostructure are defined. Experimental samples of the HEMT (with gate length 0.8 /spl mu/m) on AlGaAs/GaAs heterostructures, manufactured by MBE, are in good agreement with the simulated transistor and the discrepancy does not exceed 10%.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134518219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A relationship between structural characteristics and noise properties of thick resistive films 厚阻性薄膜结构特性与噪声特性的关系
2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI: 10.1109/ICMEL.2000.838745
I. Stanimirović, M. Jevtic, Z. Stanimirović
{"title":"A relationship between structural characteristics and noise properties of thick resistive films","authors":"I. Stanimirović, M. Jevtic, Z. Stanimirović","doi":"10.1109/ICMEL.2000.838745","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.838745","url":null,"abstract":"A relationship between structural characteristics and noise properties of thick resistive films using noise reduced mobility is presented, proving that noise index measurements can be used as an indicator in thick-film quality and reliability diagnostics. In addition, this analysis can serve as a basis for development of a new diagnostic method for thick resistive films based on noise index measurements.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117102726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The equivalent electrical model of intergranular impedance of BaTiO/sub 3/-ceramics BaTiO/sub - 3/-陶瓷晶间阻抗的等效电模型
2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400) Pub Date : 2000-05-14 DOI: 10.1109/ICMEL.2000.840568
V. Mitić, P. Petkovic, I. Mitrovic
{"title":"The equivalent electrical model of intergranular impedance of BaTiO/sub 3/-ceramics","authors":"V. Mitić, P. Petkovic, I. Mitrovic","doi":"10.1109/ICMEL.2000.840568","DOIUrl":"https://doi.org/10.1109/ICMEL.2000.840568","url":null,"abstract":"In this paper, the equivalent intergranular impedance model of BaTiO/sub 3/-ceramics is generated taking into consideration two types of connections between grains. The models are applied to a cluster of up to three spherical and polyhedral grains contacting each other. The relations between the most dominant electrical parameters (capacitance and conductance) of the intergranular microcondenser and geometric parameters are established.","PeriodicalId":215956,"journal":{"name":"2000 22nd International Conference on Microelectronics. Proceedings (Cat. No.00TH8400)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129337981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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