VHDL design validation by genetic manipulation techniques

Abstract

Formal verification is an important area in industry that gets more and more attention. The growing complexity of digital circuits and its use in safety critical systems are the reasons for the need of tools for checking the correctness of designs. In this paper we present a new approach of model evaluation. With our approach we are able to increase the belief of a designer in the right functionality of a circuit without the long runtimes of classical model checking but with more reliability than testing a design via simulation with few input patterns. To achieve this goal we use our genetic manipulation technique: a combination of classical genetic algorithms with a goal oriented mutation operator, based on a backtracking method.