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2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)最新文献

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Accurate self-heating assessment employing multi-stage thermal RC network 采用多级热RC网络进行准确的自热评定
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403838
Wangyong Chen, Linlin Cai, Kunliang Wang, Xing Zhang, Xiaoyan Liu, G. Du
{"title":"Accurate self-heating assessment employing multi-stage thermal RC network","authors":"Wangyong Chen, Linlin Cai, Kunliang Wang, Xing Zhang, Xiaoyan Liu, G. Du","doi":"10.1109/VLSI-TSA.2018.8403838","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403838","url":null,"abstract":"Multi-stage thermal RC network is extracted and verified from transient thermal response by 3D FEM simulation to accurately capture self-heating. The impact of material parameters on temperature response is investigated. Furthermore, electro-thermal analysis of devices with different thermal conductivities is implemented to study the dependence of AC frequency and power duty cycle on self-heating. The results show that self-heating is suppressed when the heating time is shorter than the time constant of substrate even if poor thermal conductivity of substrate is adopted.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127046901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Carrier conduction in SiO2/GaN structure with abrupt interface 具有突变界面的SiO2/GaN结构中的载流子传导
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403831
N. X. Truyen, N. Taoka, A. Ohta, Hisashi Yamada, Tokio Takahashi, M. Ikeda, K. Makihara, M. Shimizu, S. Miyazaki
{"title":"Carrier conduction in SiO2/GaN structure with abrupt interface","authors":"N. X. Truyen, N. Taoka, A. Ohta, Hisashi Yamada, Tokio Takahashi, M. Ikeda, K. Makihara, M. Shimizu, S. Miyazaki","doi":"10.1109/VLSI-TSA.2018.8403831","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403831","url":null,"abstract":"A monolithic GaN power integrated circuit (IC) with power devices, logic, drive, and protection circuits is a candidate system for a future low power consumption power IC. Formation of a high quality GaN MOS interface is a key for realizing the GaN Power IC. Although a good interface property of a SiO2/GaN structure have already reported[1], the SiO2/GaN structure has obvious interfacial Ga-oxide layer. On the other hand, we have established to form a SiO2/GaN interface without an obvious interfacial layer and with a low interface trap density (DIt)[2]. However, carrier conduction in the SiO2/GaN structure with the abrupt interface has not yet been investigated. In this study, characteristics of current density (J) vs oxide field (Eox) in the SiO2 layers formed by the remote-oxygen- plasma enhanced CVD (ROPE-CVD) on a GaN surface were investigated through comparisons of J-Eox characteristics between GaN and Si MOS capacitors.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132064811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
P-STT-MRAM thermal stability and modeling of its temperature dependence P-STT-MRAM热稳定性及其温度依赖性建模
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403857
L. Tillie, B. Dieny, R. Sousa, J. Chatterjee, S. Auffret, N. Lamard, J. Guelffucci, E. Nowak, I. Prejbeanu
{"title":"P-STT-MRAM thermal stability and modeling of its temperature dependence","authors":"L. Tillie, B. Dieny, R. Sousa, J. Chatterjee, S. Auffret, N. Lamard, J. Guelffucci, E. Nowak, I. Prejbeanu","doi":"10.1109/VLSI-TSA.2018.8403857","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403857","url":null,"abstract":"Due to their high speed[1], high endurance[2] and non-volatility, perpendicular STT-MRAM (P-STT-MRAM) are seen as one of the best candidate for non volatile memory embedded applications. However, their data retention time at elevated temperature such as the soldering reflow criterion and the automotive application temperature range is still a critical point. In this paper, P-STT-MRAM devices with diameters ranging from 20nm to 150nm have been tested in temperature. The thermal stability factor has been extracted electrically for temperatures up to 190°C. Then the loss in the Curie temperature of the storage layer compared to bulk values has been measured and directly linked to the thermal stability values. At last, a model is proposed to predict the temperature dependance of the thermal stability factor.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125601410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Synaptic properties considering temperature effect in HfOx-based memristor - Demonstration of homo-thermal synaptic behaviors 考虑温度效应的hfox基忆阻器的突触特性-热突触行为的演示
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403853
Jia－CHEN, Sungjun Kim, Ying‐Chen Chen, Min-Hwi Kim, Yi Li, X. Miao, Yao‐Feng Chang, Byung-Gook Park, Jack C. Lee
{"title":"Synaptic properties considering temperature effect in HfOx-based memristor - Demonstration of homo-thermal synaptic behaviors","authors":"Jia－CHEN, Sungjun Kim, Ying‐Chen Chen, Min-Hwi Kim, Yi Li, X. Miao, Yao‐Feng Chang, Byung-Gook Park, Jack C. Lee","doi":"10.1109/VLSI-TSA.2018.8403853","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403853","url":null,"abstract":"In this work, we fabricated HfOx-based RRAM-type memristors that are CMOS-compatible and analyzed its synapse characteristics. Ni/HfOx/p++Si filament-type device exhibits abrupt resistive changes in both SET and RESET operations in the same pulse response as the DC sweep, while interface-type Ni/HfOx/n++Si devices show gradual changes. Interface-type devices exhibit more dynamic states as the temperature rises, while the recognition rate of neural network using memristive synapses did not degrade for T < 145 °C. Our results suggest that neuromorphic chips fabricated using RRAM-type memristors can operate under wide temperature range.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127735273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
HEtero-layer-lift-off (HELLO) technology for enhanced hole mobility in UTB GeOI pMOSFETs 用于提高UTB GeOI pmosfet空穴迁移率的异质层提升(HELLO)技术
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403822
W. Chang, T. Irisawa, H. Ishii, H. Hattori, N. Uchida, T. Maeda
{"title":"HEtero-layer-lift-off (HELLO) technology for enhanced hole mobility in UTB GeOI pMOSFETs","authors":"W. Chang, T. Irisawa, H. Ishii, H. Hattori, N. Uchida, T. Maeda","doi":"10.1109/VLSI-TSA.2018.8403822","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403822","url":null,"abstract":"Ultra-thin-body (UTB) germanium-on-insulator (GeOI) substrates have been fabricated utilizing advanced HEtero- Layer-Lift-Off (HELLO) technology. HELLO technology is effective in mitigating thickness fluctuation issue in UTB GeOI during Ge thinning process. As a result, well-known hole mobility degradation while scaling body thickness (tbody) in UTB GeOI pMOSFETs has been suppressed. The mechanism of enhanced hole mobility in UTB GeOI pMOSFETs was also investigated through low temperature electrical measurement. The hole mobility in 9-nm-thick GeOI devices fabricated with HELLO technology showed larger temperature dependence, indicating the release of thickness fluctuation scattering.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114645742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High-mobility polymer field-effect transistor based-sensor array for selective discrimination between multiple isomers 基于高迁移率聚合物场效应晶体管的多异构体选择性鉴别传感器阵列
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403826
Muhammad Khatib, F. Hinkel, K. Müllen, H. Haick
{"title":"High-mobility polymer field-effect transistor based-sensor array for selective discrimination between multiple isomers","authors":"Muhammad Khatib, F. Hinkel, K. Müllen, H. Haick","doi":"10.1109/VLSI-TSA.2018.8403826","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403826","url":null,"abstract":"Distinguishing structural isomers and stereoisomers is a critical and challenging task for biotechnology, the pharmaceutical industry and environmental monitoring. Compared to available methods, use of the high mobility copolymer benzothiadiazole- cyclopentadithiophene (CDT-BTZ) in an OFET based gas sensor can highly selectively detect different volatile organic isomers. High- accuracy discrimination has been achieved over a range of concentrations of 20-100 ppm using only one parameter of the OFET. By analyzing the OFET parameter cross- reactivity and using differential function analysis to create fingerprints for individual compounds, more significant selectivity and robust isomer detection have been achieved.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121571421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Enhanced performance of Ag-filament threshold switching selector by rapid thermal processing 通过快速热处理提高银丝阈值开关选择器的性能
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403855
Qilin Hua, Huaqiang Wu, B. Gao, H. Qian
{"title":"Enhanced performance of Ag-filament threshold switching selector by rapid thermal processing","authors":"Qilin Hua, Huaqiang Wu, B. Gao, H. Qian","doi":"10.1109/VLSI-TSA.2018.8403855","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403855","url":null,"abstract":"Selector devices are typically employed to suppress sneak path currents in RRAM array. Here, we demonstrate a bidirectional Ag- filament threshold switching (TS) selector with an enhanced performance of large selectivity over 108 and high on-state current beyond 100 µA through rapid thermal processing (RTP). The TS selector has more than 100 M cycles endurance and can remain stable switching even when ambient temperature is up to 200°C. The mechanism of the TS selector is analyzed to explain the bidirectional selector characteristics. Indeed, this TS selector would be a good candidate for 1S1R configuration and future high-density 3D RRAM integration.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127278028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Novel patterning schemes and technologies for the sub 5nm era 亚5nm时代的新模式方案和技术
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403863
Angélique Raley, S. Thibaut, Kal Subhadeep, N. Mohanty, R. Farrell, Jeffrey T. Smith, A. Metz, Akiteru Ko, Anton DeVillier, P. Biolsi
{"title":"Novel patterning schemes and technologies for the sub 5nm era","authors":"Angélique Raley, S. Thibaut, Kal Subhadeep, N. Mohanty, R. Farrell, Jeffrey T. Smith, A. Metz, Akiteru Ko, Anton DeVillier, P. Biolsi","doi":"10.1109/VLSI-TSA.2018.8403863","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403863","url":null,"abstract":"Multipatterning has enabled continued scaling of chip technology at the 28nm logic node and beyond see Fig. 1. Self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) as well as Litho-Etch/Litho-Etch iterations are widely used in the semiconductor industry to reach sub 193 immersion lithography resolutions for critical layers such as FIN, Gate and Metal lines. Multipatterning requires the use of multiple masks, which is costly and increases process complexity as well as edge placement error variation mostly driven by overlay. In our presentation, we will propose and demonstrate novel patterning concepts, which can curb some of these downsides and usher in the next technological advancements required for further scaling. We will also survey the progress and maturity of EUV patterning in contrast to multipatterning options.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129678681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Cost-efficient sub-lithographic patterning with tilted-ion implantation (TII) 具有倾斜离子注入(TII)的低成本亚光刻图像化
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403865
Sangwan Kim, Peng Zheng, Kimihiko Kato, L. Rubin, T. Liu
{"title":"Cost-efficient sub-lithographic patterning with tilted-ion implantation (TII)","authors":"Sangwan Kim, Peng Zheng, Kimihiko Kato, L. Rubin, T. Liu","doi":"10.1109/VLSI-TSA.2018.8403865","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403865","url":null,"abstract":"A sub-lithographic patterning technique using tilted-ion implantation (TII) is discussed herein, as an approach for extending Moore's Law. Its suitability for defining patterns self-aligned to pre-existing linear and non-linear hard-mask features is demonstrated experimentally. In addition, its resolution limit (< 10 nm) and line- edge roughness (LER) are investigated via experiments as well as Monte Carlo process simulations.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114628278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Steep slope 2D negative capacitance CMOS devices: MoS2 and WSe2 陡坡2D负电容CMOS器件:MoS2和WSe2
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403843
M. Si, P. Ye
{"title":"Steep slope 2D negative capacitance CMOS devices: MoS2 and WSe2","authors":"M. Si, P. Ye","doi":"10.1109/VLSI-TSA.2018.8403843","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403843","url":null,"abstract":"This work reports steep slope sub-thermionic negative capacitance CMOS devices with 2D semiconductors as channel materials and ferroelectric hafnium zirconium oxide in the gate stack. Both n-type and p-type negative capacitance FETs are realized with MoS2 as n-type channel material and WSe2 as p-type channel material. Bidirectional sub-60 mV/dec at room temperature is achieved on both MoS2 and WSe2 negative capacitance FETs. The impact of internal metal gate on the performance of 2D negative capacitance FETs are also studied and compared with internal FETs.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134283248","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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