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2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)最新文献

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UTBSOI MOSFET with corner spacers for energy-efficient applications 带角间隔的UTBSOI MOSFET，用于节能应用
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-07-03 DOI: 10.1109/VLSI-TSA.2018.8403825
A. Sachid, C. Hu
{"title":"UTBSOI MOSFET with corner spacers for energy-efficient applications","authors":"A. Sachid, C. Hu","doi":"10.1109/VLSI-TSA.2018.8403825","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403825","url":null,"abstract":"Parasitic capacitance is a critical challenge in improving the device and circuit performance in nanoscale devices like the UTBSOI MOSFET and FinFET. Scaling the contact pitch decreases the separation between the gate and the source/drain contacts which increases the contribution of parasitic capacitance to the total capacitance as the devices are scaled. According to ITRS 2.0, the parasitic capacitance should be limited to be less than 60% of the total capacitance [1]. For sub- 20 nm node devices, introduction of source/drain underlaps improves the short-channel performance [2]. The additional resistance due to underlaps can be reduced by the introduction of higher-K spacers [3,4], and dual-K spacers trading-off parasitic capacitance [5-7]. On the other end, since air or vacuum has a dielectric constant of 1, vacuum or air-gap spacers can reduce the parasitic capacitance [8-12]. In underlapped nanoscale devices, corner spacer design in which a higher-K oxide is present only in the bottom corner of the gate and the rest of the spacer consists of a lower-K dielectric will be required to simultaneously reduce underlap resistance and parasitic capacitance [13-15]. Fig. 1 shows the different spacer design options explored such as the full spacer, dual-K spacer and corner spacer. The full spacer has a single dielectric material. The dual-K spacer has an inner higher-K and an outer lower-K dielectric. The corner spacer has a higher-K dielectric present only at the bottom corner of the gate and the rest of the spacer region is made up of a lower-K dielectric. The impact of corner spacer design on UTBSOI MOSFET has not been studied. In this paper, using TCAD simulations, we design and optimize corner spacer for UTBSOI MOSFET for the 11/10 nm node.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129741189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Electrical characteristics of gate-all-around MOSFET ring oscillators using TCAD simulation 用TCAD模拟栅极全能MOSFET环形振荡器的电学特性
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-07-03 DOI: 10.1109/VLSI-TSA.2018.8403835
Sutae Kim, Minsuk Kim, Sola Woo, Hyungu Kang, Sangsig Kim
{"title":"Electrical characteristics of gate-all-around MOSFET ring oscillators using TCAD simulation","authors":"Sutae Kim, Minsuk Kim, Sola Woo, Hyungu Kang, Sangsig Kim","doi":"10.1109/VLSI-TSA.2018.8403835","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403835","url":null,"abstract":"In this paper, we investigate the performance of inverters and ring oscillators composed of gate-all-around (GAA) silicon nanowire and nanosheet (NSH) field-effect transistors (FETs), compared with FinFETs, for sub-10nm logic technology applications. Our TCAD transient simulations reveal that ring oscillators with 3 stacked channels with NSH width, three times wider than the fin width, exhibit improvements of up to 22% in the oscillation frequencies. compared to a ring oscillator with FinFETs. Thus, our study provides an insight for device down-selection in the development of GAA FET technology.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129454722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Steep slope 2D strain field effect transistor: 2D-SFET 陡坡2D应变场效应晶体管:2D- fet
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-07-03 DOI: 10.1109/VLSI-TSA.2018.8403841
Daniel S. Schulman, Andrew J Arnold, Saptarshi Das
{"title":"Steep slope 2D strain field effect transistor: 2D-SFET","authors":"Daniel S. Schulman, Andrew J Arnold, Saptarshi Das","doi":"10.1109/VLSI-TSA.2018.8403841","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403841","url":null,"abstract":"Numerous advancements have allowed continuous aggressive dimensional scaling of CMOS to the current state of the art 10nm node but none are solutions to the fundamental Boltzmann statistics limits which have stalled Dennard voltage scaling. The semiconductor industry has invested heavily in disruptive, \"steep slope\" transistor technologies which promise lower operating voltages and dramatically reduced power consumption. While many of these technologies show great promise such as Tunnel FETs, Phase Change FETs, and even nanomechanical switches, all are far from commercialization and large-scale integration due to issues ranging from poor ON currents, limited switching ranges and reliability[4, 5].","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121615567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Integrated molecule recognition sensor electronics using nanostructured metal oxides on silicon 集成分子识别传感器电子学在硅上使用纳米结构金属氧化物
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-07-03 DOI: 10.1109/VLSI-TSA.2018.8403827
T. Yanagida
{"title":"Integrated molecule recognition sensor electronics using nanostructured metal oxides on silicon","authors":"T. Yanagida","doi":"10.1109/VLSI-TSA.2018.8403827","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403827","url":null,"abstract":"Electrical sensing of volatile molecular species in environments and/or from our bodies by using mobile electronics is an important issue for future electronic devices. This is because these sensor electronics will have an impact on our daily life and healthcare via collecting and analyzing data. Among various sensor materials, \"Metal Oxides\" is one of the most abundant and robust materials in ambient atmosphere. However, metal oxide sensors have several essential difficulties when applying to CMOS sensor electronics. Here I show our recent progress as to integrated molecule recognition sensors by utilizing nano-metal oxides [1-3] on silicon.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125205794","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Glassy-electret random access memory - A naturally nanoscale memory concept 玻璃驻极体随机存取存储器——一种天然的纳米级存储器概念
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-20 DOI: 10.1109/VLSI-TSA.2018.8403837
Vasileia Georgiou, J. Campbell, P. Shrestha, D. Ioannou, K. Cheung
{"title":"Glassy-electret random access memory - A naturally nanoscale memory concept","authors":"Vasileia Georgiou, J. Campbell, P. Shrestha, D. Ioannou, K. Cheung","doi":"10.1109/VLSI-TSA.2018.8403837","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403837","url":null,"abstract":"The self-heating effect (SHE) is a growing problem for decananometer CMOS and beyond with substantial efforts dedicated to mitigation. Here, we present a new memory concept which instead requires SHE exacerbation. As such, this memory concept is naturally suitable for extreme scaling. Preliminary result of this memory concept is demonstrated with an external heater as the SHE surrogates.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126456452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Stochastic limitations to EUV lithography EUV光刻的随机限制
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403862
C. Mack
{"title":"Stochastic limitations to EUV lithography","authors":"C. Mack","doi":"10.1109/VLSI-TSA.2018.8403862","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403862","url":null,"abstract":"Stochastic-induced roughness continues to be a major concern in the implementation of extreme ultraviolet (EUV) lithography for semiconductor high-volume manufacturing, potentially limiting product yield or lithography throughput or both. For this reason considerable effort has been made in the last 10 years to characterize, understand, and reduce stochastic-induced roughness of post- lithography and post-etch features. Despite these efforts, far too little progress has been made in reducing the effects of stochastics, such as linewidth roughness (LWR), line-edge roughness (LER), local critical dimension uniformity (LCDU), and stochastic defectivity. [1]","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"334 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123775810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A new method for test chip and single 40nm NOR Flash cell electrical parameters correlation using a CAST structure 提出了一种利用CAST结构测试芯片与单个40nm NOR闪存电池电参数相关性的新方法
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403859
T. Kempf, V. D. Marca, P. Canet, A. Régnier, P. Masson, J. Portal
{"title":"A new method for test chip and single 40nm NOR Flash cell electrical parameters correlation using a CAST structure","authors":"T. Kempf, V. D. Marca, P. Canet, A. Régnier, P. Masson, J. Portal","doi":"10.1109/VLSI-TSA.2018.8403859","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403859","url":null,"abstract":"In this work, we present a method to find a correlation between the measurements on single 40nm embedded Flash memory cell, and the 512kB test chip electrical results. The bridge between these two structures is the cell array stress test (CAST). We are able to simulate the behavior of a 10kb and a 1Mb CAST structures. The parasitic resistances are taken into account, as well as, the test chip distributions for the modeling. The aim is to reduce the time of test obtaining preliminary information concerning the fabrication process and the memory yield at the parametric test level and before the electrical wafer sorting.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134390806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
GaN-based digital transmitter architectures for 5G 基于gan的5G数字发射机架构
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-DAT.2018.8373288
Florian Huhn, A. Wentzel, W. Heinrich
{"title":"GaN-based digital transmitter architectures for 5G","authors":"Florian Huhn, A. Wentzel, W. Heinrich","doi":"10.1109/VLSI-DAT.2018.8373288","DOIUrl":"https://doi.org/10.1109/VLSI-DAT.2018.8373288","url":null,"abstract":"Fully digital transmitter chains are an important step towards the software-defined radio. Digital amplification is obtained by encoding the baseband signal into a binary bit stream and amplifying this signal with a simple switch. The wanted analog signal is restored in a simple passive band-pass filter. This paper provides a brief overview on the principle of operation, requirements, and new opportunities enabled by the use of digital transmitter chains. Recent results of research in this field are presented.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117229990","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modeling of GaN HEMTs on silicon with trapping and self-heating effects for RF applications 射频应用中具有捕获和自热效应的硅基GaN hemt的建模
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403846
Chuan-Wei Tsou, Po-tsung Tu, K. Tsai, P. Yeh, Heng-Yuan Lee, Li-heng Lee, S. Hsu
{"title":"Modeling of GaN HEMTs on silicon with trapping and self-heating effects for RF applications","authors":"Chuan-Wei Tsou, Po-tsung Tu, K. Tsai, P. Yeh, Heng-Yuan Lee, Li-heng Lee, S. Hsu","doi":"10.1109/VLSI-TSA.2018.8403846","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403846","url":null,"abstract":"In this paper, the pulsed IV, small-signal, and load-pull measurements are employed for characterization of GaN-on-Si HEMTs to establish the large-signal model for RF applications. A modified Angelov model was proposed, which achieved excellent agreement with the measured results. Both trapping and self-heating effects are identified based on the pulsed IV measurements, while the charge model are established based on small-signal measurements. Finally, the load-pull simulation and measurements were used to verify the accuracy oflarge-signal characteristics.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115421580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigation of the abrupt phase transition in 1T-TaS2/MoS2 heterostructures 1T-TaS2/MoS2异质结构中突然相变的研究
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403844
B. Grisafe, Rui Zhao, M. Jerry, J. Robinson, S. Datta
{"title":"Investigation of the abrupt phase transition in 1T-TaS2/MoS2 heterostructures","authors":"B. Grisafe, Rui Zhao, M. Jerry, J. Robinson, S. Datta","doi":"10.1109/VLSI-TSA.2018.8403844","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403844","url":null,"abstract":"Electrically induced phase transitions are being investigated for applications in steep-slope transistors, neuromorphic computing, and coupled oscillator networks. Here, we present an avenue to integrate a layered 2D phase transition material 1T-TaS<inf>2</inf> with monolayer MoS<inf>2</inf> via direct synthesis. We experimentally demonstrate that the charge density wave (CDW) based phase transition is preserved when grown directly on MoS<inf>2</inf>, however a 42% reduction in the ON/OFF ratio compared to exfoliated devices is observed. First principles calculations of the 1T-TaS<inf>2</inf>/MoS<inf>2</inf> heterostructure reveal a 39% reduction in the bandgap of 1T-TaS<inf>2</inf> compared to the free-standing 1T-TaS<inf>2</inf> case.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132890988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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