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2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)最新文献

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Temperature and stress effect of random telegraph noise in FIND RRAM arrays FIND随机随机存储器阵列中随机电报噪声的温度和应力效应
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403834
Chin Yuan Chen, C. Lin, Y. King
{"title":"Temperature and stress effect of random telegraph noise in FIND RRAM arrays","authors":"Chin Yuan Chen, C. Lin, Y. King","doi":"10.1109/VLSI-TSA.2018.8403834","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403834","url":null,"abstract":"An observation on random telegraph noise (RTN) signal in the read current of a FinFET Dielectric RRAM (FIND RRAM) device is presented in this work. The RTN signal of a FIND RRAM cell is found to change with stress and ambient temperature. Cells with more cycling stress show a stronger tendency to exhibit RTN signals. RTN signals in FIND cells can be generally alleviated by high temperature anneal, and an on chip annealing scheme is proposed and demonstrated.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"295 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134313654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel solutions to enable contact resistivity <1E-9 Ω-cm2 for 5nm node and beyond 新颖的解决方案，使5nm节点及以上的接触电阻率<1E-9 Ω-cm2
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403817
R. Hung, F. Khaja, K. Hollar, K. Rao, S. Munnangi, Yongmei Chen, M. Okazaki, Yi-Chiau Huang, Xuebin Li, Hua Chung, O. Chan, C. Lazik, M. Jin, Hongwen Zhou, A. Mayur, Namsung Kim, E. Yieh
{"title":"Novel solutions to enable contact resistivity <1E-9 Ω-cm2 for 5nm node and beyond","authors":"R. Hung, F. Khaja, K. Hollar, K. Rao, S. Munnangi, Yongmei Chen, M. Okazaki, Yi-Chiau Huang, Xuebin Li, Hua Chung, O. Chan, C. Lazik, M. Jin, Hongwen Zhou, A. Mayur, Namsung Kim, E. Yieh","doi":"10.1109/VLSI-TSA.2018.8403817","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403817","url":null,"abstract":"In this paper, we present a solution for N&P MOS contact resistivity (p<inf>c</inf>) improvement by adoption of highly doped epitaxial source/drain (S/D), contact ion implantation and advanced laser anneal. An ultra-low ρ<inf>c</inf> =3D 9.01x10<sup>-10</sup> Ωcm<sup>2</sup> on NMOS contact chain (CC) is achieved using highly doped (HD) Si:P selective epi in S/D combined with Ge PAI (pre-amorphization implant) and Applied Materials' nanosecond laser anneal (NLA). In addition, a record low ρ<inf>c</inf> =3D 1.16 x10<sup>-9</sup> Ωcm<sup>2</sup> for PMOS CC is demonstrated by Si<inf>0.55</inf>Ge<inf>045</inf>:B epi, Ga cryo ion implant and NLA. NLA enables super-activation of implanted dopants and dopants in the in-situ HD S/D epi films ([P]: 3.0x10<sup>21</sup>cm<sup>-3</sup> for NSD epi; [B]: 1.0x10<sup>21</sup>cm<sup>-3</sup> for PSD epi). These new process technologies provide a pathway to achieve the target p<inf>c</inf> required for transistor performance in advanced logic devices.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126372271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Modeling of SOI uniformity impact on silicon photonic grating coupler performance compared to other process variation sources 模拟SOI均匀性对硅光子光栅耦合器性能的影响，并与其他工艺变化源进行比较
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403833
G. Gaudin, D. Fowler, Celine Cailler, A. Rigny
{"title":"Modeling of SOI uniformity impact on silicon photonic grating coupler performance compared to other process variation sources","authors":"G. Gaudin, D. Fowler, Celine Cailler, A. Rigny","doi":"10.1109/VLSI-TSA.2018.8403833","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403833","url":null,"abstract":"Silicon Photonics is a unique platform for optical component integration that will provide high-data rate and cost-effective solutions for data center interconnections of 40 Gbps and beyond. High data rates and low levels of optical losses are key indicators for optical performance. Silicon on Insulator substrates are the preferred choice for silicon photonics as they allow easy manufacturing of uniformly thick waveguides for the fabrication of optical devices such as integrated 4 channel WDM transceivers [1]. Uniformity of the SOI layer is a key parameter to ensure the lowest total circuit optical loss, while a thick buried oxide guarantees a good optical confinement. The effect of typical SOI uniformity has been considered among other parameters as a factor impacting optical device performance by many research groups [2-4].","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127999436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A new high voltage IC with robust isolation design 一种新型高压集成电路，具有强大的隔离设计
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-TSA.2018.8403845
V. Ningaraju, Horng-Chih Lin, Po-An Chen, Ji Wen
{"title":"A new high voltage IC with robust isolation design","authors":"V. Ningaraju, Horng-Chih Lin, Po-An Chen, Ji Wen","doi":"10.1109/VLSI-TSA.2018.8403845","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403845","url":null,"abstract":"A new and robust isolation design for control devices integrated in the high side island region of 250V high-voltage integrated circuits (HVIC) is proposed and verified by numerical calculations, simulations and experiments. The new isolation structure can be realized using micro N-well in the P-type isolation region to achieve a higher breakdown voltage (BV). The measurement and TCAD simulation results prove this new isolation structure's BV is over 350V with negligible leakage current. In the proposed scheme BV is improved by 15% more than the conventional structure without adding additional process steps and photo layers.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129370803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Antenna-in-package design and module integration for millimeter-wave communication and 5G 毫米波通信和5G的封装天线设计和模块集成
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 1900-01-01 DOI: 10.1109/vlsi-dat.2018.8373286
X. Gu, B. Sadhu, Duixian Liu, C. Baks, A. Valdes-Garcia
{"title":"Antenna-in-package design and module integration for millimeter-wave communication and 5G","authors":"X. Gu, B. Sadhu, Duixian Liu, C. Baks, A. Valdes-Garcia","doi":"10.1109/vlsi-dat.2018.8373286","DOIUrl":"https://doi.org/10.1109/vlsi-dat.2018.8373286","url":null,"abstract":"Co-design and integration of RFIC, package, and antennas are critical to enable 5G wireless communications and is particularly challenging at mmWave frequencies. This paper reviews two different aspects of mmWave antenna module packaging and integration for base station and user equipment applications, respectively. We first present the challenges, implementation, and characterization of a 28­GHz phased-array module with 64 dual polarized antennas for 5G base station applications. Next, we describe a compact, low-power, 60-GHz switched-beam transceiver module suitable for handset integration incorporating 4 antennas that supports both normal and end-fire directions for a wide link spatial coverage.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114832351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Interface discrete trap induced variability for negative capacitance FinFETs 负电容finfet的界面离散陷阱诱导可变性
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-TSA.2018.8403836
Ho-Pei Lee, Kuei-Yang Tseng, P. Su
{"title":"Interface discrete trap induced variability for negative capacitance FinFETs","authors":"Ho-Pei Lee, Kuei-Yang Tseng, P. Su","doi":"10.1109/VLSI-TSA.2018.8403836","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403836","url":null,"abstract":"To fulfill the future need of ultra-low-power applications such as Internet-of-Things (IoT) technologies [1], steep-slope transistors are indispensable. Negative capacitance FET (NCFET) is one of the most promising steep-slope devices because it may possess sub-kT/q swing and high on/off current ratio simultaneously [2]. For scaled devices especially under low voltage operation, statistical variation is one ma­jor concern. The random variation may stem from intrinsic variations and discrete interface charges [3], [4]. The impact of the interface charge can also be an indication of the bias temperature instability (BTI) responsible for the time-dependent transistor degradation [5]. The research related to the impact of interface traps on the NCFET is still lacking and merits investigation. In this work, through atomistic TCAD simulation, we investigate the interface discrete trap induced variability for negative capacitance FinFETs (NC-FinFETs).","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116463561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Emerging technologies and concepts for 5G applications — A. making additive manufactured ceramic microwave filters ready for 5G 5G应用的新兴技术和概念- A.为5G准备增材制造的陶瓷微波滤波器
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 1900-01-01 DOI: 10.1109/vlsi-dat.2018.8373287
S. Sattler, F. Gentili, R. Teschl, C. Carceller, W. Bösch
{"title":"Emerging technologies and concepts for 5G applications — A. making additive manufactured ceramic microwave filters ready for 5G","authors":"S. Sattler, F. Gentili, R. Teschl, C. Carceller, W. Bösch","doi":"10.1109/vlsi-dat.2018.8373287","DOIUrl":"https://doi.org/10.1109/vlsi-dat.2018.8373287","url":null,"abstract":"Additive manufacturing (AM) techniques for filter applications have proven to be vital in enabling a variety of forms and shapes best suitable for 5G application. However, in order to guarantee a good RF performance of the passive components, certain aspects have to be taken into account. When it comes to dielectric resonators manufactured in ceramic AM, the quality of the metallization is crucial. Based on a simple prototype, this paper reports on the performance when using an advanced coating technique applied to a 3D printed ceramic body.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122317236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A new and simple DC method for thermal-resistance extraction of scaled FinFET devices 一种新的、简单的直流方法提取缩放FinFET器件的热阻
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-TSA.2018.8403832
Wei-Cheng Huang, P. Su
{"title":"A new and simple DC method for thermal-resistance extraction of scaled FinFET devices","authors":"Wei-Cheng Huang, P. Su","doi":"10.1109/VLSI-TSA.2018.8403832","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403832","url":null,"abstract":"This work proposes a new and simple hot-chuck measurement method for the extraction of the thermal resistance of FinFETs. The intrinsic transconductance that eliminates the parasitic source/drain resistance effect can serve as a temperature sensor to characterize the device temperature rise due to self-heating. Our method requires only DC measurements without the need of special test structures.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116811258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Excellent high temperature retention of TiOxNy ReRAM by interfacial layer engineering 界面层工程制备了优异的TiOxNy ReRAM高温保持性
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-TSA.2018.8403851
Yu-Hsuan Lin, Dai-Ying Lee, Chao-Hung Wang, Ming-Hsiu Lee, Y. Ho, E. Lai, K. Chiang, H. Lung, Keh-Chung Wang, T. Tseng, Chih-Yuan Lu
{"title":"Excellent high temperature retention of TiOxNy ReRAM by interfacial layer engineering","authors":"Yu-Hsuan Lin, Dai-Ying Lee, Chao-Hung Wang, Ming-Hsiu Lee, Y. Ho, E. Lai, K. Chiang, H. Lung, Keh-Chung Wang, T. Tseng, Chih-Yuan Lu","doi":"10.1109/VLSI-TSA.2018.8403851","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403851","url":null,"abstract":"Since the resistance switching of the transition metal oxide (TMO) resistive random access memory (ReRAM) is based on the interaction between the oxygen ions and vacancies, the unintentional oxygen/vacancy reaction should be avoided during data retention. This work demonstrates significant improvements on the retention performance by inserting a Si layer in the TiOxNy ReRAM to block the diffusion of oxygen ions through the Ti/TiOxNy interface. The mechanism and factors that influenced the HRS and LRS retention are also studied. The retention performance of HRS is correlated with its RESET level while the LRS retention depends on the programming current. The proposed Ti/Si/TiOxNy ReRAMs can switch for more than 103 cycles from array testing results.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132582814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel rewritable one-time-programming OTP (RW-OTP) realized by dielectric-fuse RRAM devices featuring ultra-high reliable retention and good endurance for embedded applications 一种新型的可重写一次性编程OTP (RW-OTP)，采用介电保险丝RRAM器件实现，具有超高的可靠性保持和良好的耐用性，适用于嵌入式应用
2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 1900-01-01 DOI: 10.1109/VLSI-TSA.2018.8403852
H. W. Cheng, E. Hsieh, Z. H. Huang, C. Chuang, C. Chen, F. L. Li, Y. Lo, C. H. Liu, S. Chung
{"title":"A novel rewritable one-time-programming OTP (RW-OTP) realized by dielectric-fuse RRAM devices featuring ultra-high reliable retention and good endurance for embedded applications","authors":"H. W. Cheng, E. Hsieh, Z. H. Huang, C. Chuang, C. Chen, F. L. Li, Y. Lo, C. H. Liu, S. Chung","doi":"10.1109/VLSI-TSA.2018.8403852","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403852","url":null,"abstract":"A novel concept of OTP has been demonstrated to create another feasibility to allow re-writable capability before storing the data. This OTP is named Rewritable One-time- programming (RW-OTP) memory. With RW-OTP, users can do the test by modifying the contexts repeatedly before finalizing the stored data. To implement the memory cell, it consists of a gate-floated FinFET and an RRAM where a bilayer has been designed as a thicker dielectric layer with resistive-switching property on a thinner dielectric-fuse layer. Moreover, the process of RW-OTP is fully compatible with the state-of- the-art CMOS logic technology. The result shows that the memory cell exhibits high retention and good endurance. With proper use of RW-OTP, the users can not only reduce error jobs cost-efficiently but also can develop various applications for their needs. This memory cell is very promising for embedded applications.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128440518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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