新颖的解决方案，使5nm节点及以上的接触电阻率<1E-9 Ω-cm2

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI:10.1109/VLSI-TSA.2018.8403817

R. Hung, F. Khaja, K. Hollar, K. Rao, S. Munnangi, Yongmei Chen, M. Okazaki, Yi-Chiau Huang, Xuebin Li, Hua Chung, O. Chan, C. Lazik, M. Jin, Hongwen Zhou, A. Mayur, Namsung Kim, E. Yieh

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引用次数: 6

摘要

本文提出了采用高掺杂外延源/漏极(S/D)、接触离子注入和先进激光退火技术来提高N&P MOS接触电阻率(pc)的解决方案。采用高掺杂(HD) Si:P选择性外接体与Ge PAI(预非晶化植入物)和应用材料公司的纳秒激光退火(NLA)相结合，在S/D中实现了NMOS接触链(CC)上的超低ρc =3D 9.01x10-10 Ωcm2。此外，通过Si0.55Ge045:B epi、Ga冷离子注入和NLA，证明了PMOS CC的ρc =3D 1.16 x10-9 Ωcm2的新低。NLA可以使植入的掺杂剂和原位HD S/D外延膜中的掺杂剂超活化(NSD外延膜:3 × 1021cm-3;[B]: 1 × 1021cm-3 (PSD)。这些新的工艺技术为实现先进逻辑器件中晶体管性能所需的目标pc提供了一条途径。

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Novel solutions to enable contact resistivity <1E-9 Ω-cm2 for 5nm node and beyond

In this paper, we present a solution for N&P MOS contact resistivity (pc) improvement by adoption of highly doped epitaxial source/drain (S/D), contact ion implantation and advanced laser anneal. An ultra-low ρc =3D 9.01x10^-10 Ωcm² on NMOS contact chain (CC) is achieved using highly doped (HD) Si:P selective epi in S/D combined with Ge PAI (pre-amorphization implant) and Applied Materials' nanosecond laser anneal (NLA). In addition, a record low ρc =3D 1.16 x10^-9 Ωcm² for PMOS CC is demonstrated by Si0.55Ge045:B epi, Ga cryo ion implant and NLA. NLA enables super-activation of implanted dopants and dopants in the in-situ HD S/D epi films ([P]: 3.0x10²¹cm^-3 for NSD epi; [B]: 1.0x10²¹cm^-3 for PSD epi). These new process technologies provide a pathway to achieve the target pc required for transistor performance in advanced logic devices.

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2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

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