Interface discrete trap induced variability for negative capacitance FinFETs

To fulfill the future need of ultra-low-power applications such as Internet-of-Things (IoT) technologies [1], steep-slope transistors are indispensable. Negative capacitance FET (NCFET) is one of the most promising steep-slope devices because it may possess sub-kT/q swing and high on/off current ratio simultaneously [2]. For scaled devices especially under low voltage operation, statistical variation is one ma­jor concern. The random variation may stem from intrinsic variations and discrete interface charges [3], [4]. The impact of the interface charge can also be an indication of the bias temperature instability (BTI) responsible for the time-dependent transistor degradation [5]. The research related to the impact of interface traps on the NCFET is still lacking and merits investigation. In this work, through atomistic TCAD simulation, we investigate the interface discrete trap induced variability for negative capacitance FinFETs (NC-FinFETs).