2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)最新文献_第2页

ZnON contacts enabling high-performance 3-D InGaZnO inverters ZnON触点支持高性能3-D InGaZnO逆变器

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403819

Chin-I Kuan, K. Peng, Horng-Chih Lin, Pei-Wen Li

引用次数: 0

BEOL compatible sub-nm diffusion barrier for advanced Cu interconnects 先进铜互连的BEOL兼容亚纳米扩散势垒

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403818

Chun-Li Lo, Kehao Zhang, J. Robinson, Zhihong Chen

{"title":"BEOL compatible sub-nm diffusion barrier for advanced Cu interconnects","authors":"Chun-Li Lo, Kehao Zhang, J. Robinson, Zhihong Chen","doi":"10.1109/VLSI-TSA.2018.8403818","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403818","url":null,"abstract":"The limit of diffusion barrier/liner thickness scaling is one of the main challenges in modern Cu interconnect technology. Since conventional diffusion barriers are much more resistive than Cu, their thickness needs to be as thin as possible to achieve overall lower line resistance. However, these barrier materials lose their ability to block Cu diffusion when they are extremely scaled, as illustrated in Fig. 1. Therefore, sub-nm barrier is urgently demanded for ultra-scaled interconnects in the near future. To address this issue, 2D layered materials have been proposed and tested as diffusion barrier alternatives because of their atomically thin body thickness. Promising results showing improved interconnect performance have been achieved in these materials (Table I). For example, with a graphene passivation, Cu resistivity at scaled dimensions has been reduced [1] and electromigration can be alleviated [2]. Moreover, studies have shown that 2D layered materials have superior diffusion barrier properties [3]- [6]. Despite the abovementioned benefits of 2D layered materials, a BEOL compatible growth process that can directly deposit on dielectrics and is adaptable to damascene structures still needs to be demonstrated (Fig. 2). In this work, single-layer molybdenum disulfide (1L MoS2; 0.615 nm) directly grown on SiO2 at 400 °C is achieved by metal-organic chemical vapor deposition (MOCVD). We will show that this sub-nm barrier can effectively prevent Cu diffusion, and is able to reduce Cu resistivity.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128036532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Hafnium oxide based ferroelectric devices for memories and beyond 用于记忆及其他用途的氧化铪基铁电器件

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403848

T. Mikolajick, U. Schroeder, S. Slesazeck

{"title":"Hafnium oxide based ferroelectric devices for memories and beyond","authors":"T. Mikolajick, U. Schroeder, S. Slesazeck","doi":"10.1109/VLSI-TSA.2018.8403848","DOIUrl":"https://doi.org/10.1109/VLSI-TSA.2018.8403848","url":null,"abstract":"Ferroelectricity is a material property were a remanent polarization exists under zero electrical field that can be reversed by applying an electrical field [1]. As consequence, two nonvolatile states exist that can be switched by an electrical field. This feature makes ferroelectrics ideally suited for nonvolatile memories with low write energy. Therefore, already in the 1950s first attempts have been made to realize ferroelectric nonvolatile memories based on ferroelectric barium titanate (BTO) crystals having evaporated electrodes on both sides [2]. The success of this approach was hindered by disturb issues that could be solved in the early 1990s by adding a transistor device as a selector [3]. Such a memory is referred to as a ferroelectric random access memory (FeRAM). Since reading of the ferroelectric polarization from a capacitor requires switching of the ferroelectric [1], the information will be destroyed and a write back is necessary. This can be avoided if the ferroelectric is placed inside of the gate stack of a MOS transistor resulting in a ferroelectric field effect transistor (FeFET) [1]. Conventional ferroelectric materials like BTO or lead- zirconium titanate (PZT) cannot be placed directly on silicon since unwanted interface reactions will occur. The necessary interface layer together with the space charge region of the transistor device leads to a rather low capacitance in series with the ferroelectric dielectric and consequently results in a strong depolarization field that has destroyed the nonvolatility of the FeFET device for many years and hinters scaling as well [4]. Today FeRAM devices are established on the market [3,5], but are limited to niche application since scaling is hindered by many integration problems associated to materials like PZT.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"26 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123275836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Damageless and conformai doping for FinFETs by spin-coated phosphorus doped silica 自旋包覆磷掺杂二氧化硅的finfet无损共形掺杂

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403820

T. Matsukawa, T. Mori, Y. Sawada, Y. Kinoshita, Yongxun Liu, M. Masahara

引用次数: 0

All optical NOR gate via tunnel-junction transistor lasers for high speed optical logic processors 全光NOR门通过隧道结晶体管激光器用于高速光学逻辑处理器

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403847

M. Feng, Ardy Winoto, Junyi Qiu, Yuefeng Peng, N. Holonyak

引用次数: 4

Investigation of self-heating effect on stacked nanosheet GAA transistors 堆叠纳米片GAA晶体管的自热效应研究

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403821

Linlin Cai, Wangyong Chen, G. Du, Jinfeng Kang, Xing Zhang, Xiaoyan Liu

引用次数: 10

Approaches and opportunities for area-selective atomic layer deposition 区域选择性原子层沉积的方法和机会

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403864

A. Mackus

引用次数: 2

Towards high density STT-MRAM at sub-20nm nodes 迈向20nm以下节点的高密度STT-MRAM

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-16 DOI: 10.1109/VLSI-TSA.2018.8403867

V. Nguyen, N. Perrissin, S. Lequeux, J. Chatterjee, L. Tille, S. Auffret, R. Sousa, E. Gautier, L. Vila, L. Prejbeanu, B. Dieny

引用次数: 5

Novel IrOx/SiO2/W cross-point memory for lysyl-oxidase-like-2 (LOXL2) breast cancer biomarker detection 新型IrOx/SiO2/W交叉点存储器用于赖氨酸氧化酶样2 (LOXL2)乳腺癌生物标志物检测

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403860

S. Jana, S. Samanta, S. Roy, J. Qiu, S. Maikap

引用次数: 0

Mobility calculation of Ge nanowire junctionless NFETs with size and geometry dependence 考虑尺寸和几何关系的Ge纳米线无结非场效应管迁移率计算

2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2018-04-01 DOI: 10.1109/VLSI-TSA.2018.8403824

Hung-Yu Ye, Chia-Che Chung, I-Hsieh Wong, H. Lan, C. Liu

引用次数: 1