{"title":"区域选择性原子层沉积的方法和机会","authors":"A. Mackus","doi":"10.1109/VLSI-TSA.2018.8403864","DOIUrl":null,"url":null,"abstract":"With conventional semiconductor fabrication based on top-down processing reaching its limits in terms of patterning resolution and alignment, there is increasing interest in the implementation of bottom-up fabrication steps. In this contribution, several approaches for bottom-up processing by area-selective atomic layer deposition (ALD) will be reviewed, and the application possibilities and the main challenges in the field will be discussed.","PeriodicalId":209993,"journal":{"name":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Approaches and opportunities for area-selective atomic layer deposition\",\"authors\":\"A. Mackus\",\"doi\":\"10.1109/VLSI-TSA.2018.8403864\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With conventional semiconductor fabrication based on top-down processing reaching its limits in terms of patterning resolution and alignment, there is increasing interest in the implementation of bottom-up fabrication steps. In this contribution, several approaches for bottom-up processing by area-selective atomic layer deposition (ALD) will be reviewed, and the application possibilities and the main challenges in the field will be discussed.\",\"PeriodicalId\":209993,\"journal\":{\"name\":\"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)\",\"volume\":\"85 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-04-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-TSA.2018.8403864\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2018.8403864","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Approaches and opportunities for area-selective atomic layer deposition
With conventional semiconductor fabrication based on top-down processing reaching its limits in terms of patterning resolution and alignment, there is increasing interest in the implementation of bottom-up fabrication steps. In this contribution, several approaches for bottom-up processing by area-selective atomic layer deposition (ALD) will be reviewed, and the application possibilities and the main challenges in the field will be discussed.