A new method for test chip and single 40nm NOR Flash cell electrical parameters correlation using a CAST structure

Abstract

In this work, we present a method to find a correlation between the measurements on single 40nm embedded Flash memory cell, and the 512kB test chip electrical results. The bridge between these two structures is the cell array stress test (CAST). We are able to simulate the behavior of a 10kb and a 1Mb CAST structures. The parasitic resistances are taken into account, as well as, the test chip distributions for the modeling. The aim is to reduce the time of test obtaining preliminary information concerning the fabrication process and the memory yield at the parametric test level and before the electrical wafer sorting.