2006 IEEE International Symposium on Power Semiconductor Devices and IC's最新文献

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V-JFET Transistors for over voltage protection in power device series connected applications 在功率器件串联应用中过压保护的V-JFET晶体管
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666119
L. Vincent, B. Nguyen-Dac, J. Crebier, F. Alkayal, C. Schaeffer
{"title":"V-JFET Transistors for over voltage protection in power device series connected applications","authors":"L. Vincent, B. Nguyen-Dac, J. Crebier, F. Alkayal, C. Schaeffer","doi":"10.1109/ISPSD.2006.1666119","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666119","url":null,"abstract":"Nowadays, MOSFET and IGBT components are widely used in medium and high power converters. They are subjected to increasing requirements: electrical performances, simple implementation, reliability, integration, smaller volume and price. Moreover, their integration process offers the possibility to reduce and to eliminate the need for pick and place, bonding (wafer-and/or ball-bonding) and other assembly processes necessary in hybrid assemblies, and in the same time to add some useful functionality like sensors for protection and control. This paper presents a possible solution for the monolithic integration of over voltage protection circuits for power MOSFETs or IGBTs. The solution contains a vertical JFET transistor, integrated together, in the same die, with the main switch (MOSFET/IGBT). The specific characteristic of vertical JFET with diffused gates is used to control over voltage and voltage balance among devices associated in series connection. Thanks to voltage threshold control, the voltage protection level can be adjusted under operation. This new feature allows modifying the protection level and smoothness thanks to operating conditions. It allows redistributing voltage balance when one of several units, in the series connection, is out of operation, allowing the operation under failure mode operation. In addition, switching smoothness can also be adjusted thanks to VJFET control sensitivity. The paper presents the power electronic application fields. Then, vertical JFET operation and characteristics will be recalled. It is shown how it can be used for over voltage management. Two solutions are presented. One of them is studied and experimented to highlight the operation principles. Experimental results are provided based on prototypes realized, including a power MOSFET and a V-JFET within the same voltage terminations. Monolithic integration conditions are briefly addressed","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116995666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
1200V Interconnection Technique with Isolated Self-Shielding Structure 具有隔离自屏蔽结构的1200V互连技术
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666148
Sunglyong Kim, C. Jeon, Min-Suk Kim, Jong-jib Kim
{"title":"1200V Interconnection Technique with Isolated Self-Shielding Structure","authors":"Sunglyong Kim, C. Jeon, Min-Suk Kim, Jong-jib Kim","doi":"10.1109/ISPSD.2006.1666148","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666148","url":null,"abstract":"1200V interconnection technique with the isolated self-shielding concept was verified by simulation and realized without big process changes from the 600V HVIC process conditions. P-substrate resistivity, p-isolation dose, and interlayer thickness, which relieve the electric field under HV interconnection metal line, are found to be the main factors determining breakdown voltage. Experimental results have shown that over 1200V of breakdown voltage without isolation leakage current can be obtained when the p-substrate resistivity of 200ohm.cm and the p-isolation dose of 8.0e12cm-2 are used","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"322 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122166545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Two-Carrier Current Saturation in a Lateral Dmos 横向Dmos中的双载流子电流饱和
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666078
J. Lin, P. Hower
{"title":"Two-Carrier Current Saturation in a Lateral Dmos","authors":"J. Lin, P. Hower","doi":"10.1109/ISPSD.2006.1666078","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666078","url":null,"abstract":"Conventional Ldmos transistors suffer from drain current \"compression\" in saturation (gm reduction). When the safe-operating area of the Ldmos is improved by suppressing the parasitic bipolar transistor, an unusual \"expansion\" in the drain characteristic emerges. This new device behavior is described and a mechanism for the \"expansion\" proposed","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117230209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Novel Enhanced-Planar IGBT Technology Rated up to 6.5kV for Lower Losses and Higher SOA Capability 新型增强型平面IGBT技术,额定电压高达6.5kV,具有更低的损耗和更高的SOA能力
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666064
Munaf T. A. Rahimo, A. Kopta, S. Linder
{"title":"Novel Enhanced-Planar IGBT Technology Rated up to 6.5kV for Lower Losses and Higher SOA Capability","authors":"Munaf T. A. Rahimo, A. Kopta, S. Linder","doi":"10.1109/ISPSD.2006.1666064","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666064","url":null,"abstract":"In this paper, we introduce an IGBT planar technology, which sets a new performance benchmark in terms of losses and SOA capability. The improved trade-off relationship between on-state losses Vce(sat) and turn-off losses Eoff (i.e. technology curve) was solely realized by means of planar cell enhancement. Simultaneously, high levels of turn-off ruggedness (RBSOA) were obtained with the new cell design. The enhanced-planar IGBT technology is implemented on the soft-punch-through (SPT) buffer concept for ensuring controllable and soft switching behaviour. The paper covers design details of the enhanced-planar technology and a full set of results for the 6500V EP-IGBT chip","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"302 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128170564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 76
Problems on the SRH Recombination Model and a Proposed Solution SRH重组模型的若干问题及解决方法
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666104
I. Takata
{"title":"Problems on the SRH Recombination Model and a Proposed Solution","authors":"I. Takata","doi":"10.1109/ISPSD.2006.1666104","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666104","url":null,"abstract":"It's common that the present device simulator has a trouble to handle the life times in bipolar devices. However, the author could reproduce the JF-VF characteristics of some high speed pin diodes by including the radiative recombination. The simple SRH recombination model could not explain the JF-VF characteristics but also the JR-V R characteristics of pin diodes. Although the radiative recombination has been neglected in indirect semiconductors, the author would suggest the all types of recombination mechanisms, that are proportional to the carrier densities to the powered of one, two and three. And, the first one would contain a new powerful mechanism than the SRH's","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127127699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A new Principle for a Self-Protecting Power Transistor Array Design 一种自保护型功率晶体管阵列设计新原理
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666079
V. Vashchenko, P. Hopper
{"title":"A new Principle for a Self-Protecting Power Transistor Array Design","authors":"V. Vashchenko, P. Hopper","doi":"10.1109/ISPSD.2006.1666079","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666079","url":null,"abstract":"A new device level ESD protection solution for high-voltage NLDMOS power arrays is proposed and experimentally evaluated. Contrary to a conventional local clamp approach this new concept provides a self-protection capability within the array itself. The self-protecting capability of the NLDMOS array is achieved by embedding within some of the array fingers, a series of distributed diffusion regions that form an additional parasitic SCR structure with reversible snapback capabilities","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126383780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
TherMos3: a 3D electrothermal simulator for Smart Power Devices TherMos3:用于智能电源设备的3D电热模拟器
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666109
A. Irace, G. Breglio, P. Spirito
{"title":"TherMos3: a 3D electrothermal simulator for Smart Power Devices","authors":"A. Irace, G. Breglio, P. Spirito","doi":"10.1109/ISPSD.2006.1666109","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666109","url":null,"abstract":"In this paper, we report on a novel simulation tool designed for the 3D coupled electro-thermal simulation of smart power devices, that is a tool capable of taking into account not only the electrical (and thermal) behaviour of the power device but also the different driving strategies as they are imposed by a control logic circuit which usually resides on the same chip. To validate the proposed approach, simulator results are compared to experimental data obtained on a commercial smart power device used in automotive applications","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"309 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122971525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Complementary RF-LDMOS Architecture Compatible with 0.13μm CMOS Technology 兼容0.13μm CMOS技术的互补RF-LDMOS架构
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666065
N. Mohapatra, H. Ruecker, K. Ehwald, R. Sorge, R. Barth, P. Schley, D. Schmidt, H. Wulf
{"title":"A Complementary RF-LDMOS Architecture Compatible with 0.13μm CMOS Technology","authors":"N. Mohapatra, H. Ruecker, K. Ehwald, R. Sorge, R. Barth, P. Schley, D. Schmidt, H. Wulf","doi":"10.1109/ISPSD.2006.1666065","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666065","url":null,"abstract":"In this paper, we present a modular and reliable complementary RF LDMOS (laterally diffused MOS) architecture fully compatible with a 0.13 mum CMOS platform. We demonstrate BVDS*fT values up to 560 and 210 GHzV, respectively, for N- and PLDMOS transistors. A major advantage of the proposed process flow is that the drift region of N- and PLDMOS transistors can be independently optimized for different BVDSwithout affecting the VT","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122679966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Future Trend of Flat Panel Displays and Comparison of its Driving Methods 平板显示器的未来趋势及其驱动方式的比较
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666053
S. Uchikoga
{"title":"Future Trend of Flat Panel Displays and Comparison of its Driving Methods","authors":"S. Uchikoga","doi":"10.1109/ISPSD.2006.1666053","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666053","url":null,"abstract":"This paper reviews principles and driving methods for various type of flat panel displays (FPDs), such as liquid crystal displays (LCDs), organic light emitting displays (OLEDs) and plasma display panels (PDPs). For long time, Cathode ray tubes (CRTs) including CRT projection displays were the only device capable of exhibiting moving picture images applicable to TV receivers. To improve bulky and heavy structure of CRT, FPDs have been developed and are now available in the market. LCDs created various applications of displays, because of its size variation and high-resolution capability. It is essential to understand the operational principle of the display in order to meet the needs. The need of high image quality is increasing and the demand of portability is also increasing as visual information is provided in various media other than TV broadcasting. It is important to optimize the display specifications according to its application. There is a trend of adding new value to the display such as integrating input function and flexibility. The review also includes newly introduced surface conduction electron emitter displays (SEDs). Furthermore, this paper introduces aspects of future displays and trends in terms of specifications","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121871850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Integrated Over Voltage Protection Circuits for Power Transistors 功率晶体管集成过压保护电路
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666116
F. Alkayal, J. Crebier, C. Schaeffer
{"title":"Integrated Over Voltage Protection Circuits for Power Transistors","authors":"F. Alkayal, J. Crebier, C. Schaeffer","doi":"10.1109/ISPSD.2006.1666116","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666116","url":null,"abstract":"Nowadays, MOSFET and IGBT power components are widely used in medium and high power converters. They are subjected to increasing requirements: electrical performances, simple implementation, reliability, integration, smaller volume and price. Moreover, their integration process offers the possibility to reduce or eliminate the need for pick and place, bonding (wafer- and/or ball-bonding) and other assembly processes necessary in hybrid assemblies, and in the same time to add some useful functionality like sensors for protection and control. This paper presents an overview of integrated solutions for active over voltage protection circuits. A short state of the art presents the main integrated topologies and compares them. Technological, electrical and thermal compatibilities and interactions are investigated in order to outline what are the benefits but also the limitations of over voltage protection circuit integration. In particular, this analysis tries to evaluate the thermal impact of the protection circuit, which is a dissipative element, on the integrated die and the power switch. Monolithic and hybrid interconnects are also considered in the paper to outline possible benefits from the integration. Several results from simulations but also practice are available in the paper to validate comments and conclusions","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"2016 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128056196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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