A new Principle for a Self-Protecting Power Transistor Array Design

Abstract

A new device level ESD protection solution for high-voltage NLDMOS power arrays is proposed and experimentally evaluated. Contrary to a conventional local clamp approach this new concept provides a self-protection capability within the array itself. The self-protecting capability of the NLDMOS array is achieved by embedding within some of the array fingers, a series of distributed diffusion regions that form an additional parasitic SCR structure with reversible snapback capabilities