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Analysis of Dynamic Avalanche Phenomenon of PiN Diode Using He Ion Irradiation He离子辐照引脚二极管动态雪崩现象分析
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666092
T. Misumi, S. Nakagaki, M. Yamaguchi, K. Sugiyama, F. Hirahara, K. Nishiwaki
{"title":"Analysis of Dynamic Avalanche Phenomenon of PiN Diode Using He Ion Irradiation","authors":"T. Misumi, S. Nakagaki, M. Yamaguchi, K. Sugiyama, F. Hirahara, K. Nishiwaki","doi":"10.1109/ISPSD.2006.1666092","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666092","url":null,"abstract":"The purpose of this paper is to analyze the dynamic avalanche phenomenon of conventional PiN diodes using He ion irradiation. In conventional PiN diodes, the avalanche occurs during reverse recovery operation under high voltage and low temperature conditions, resulting in two peaks and high frequency oscillation in the recovery current. The two peaks in the current were reproduced by a simulation that introduces hole trap levels. It was also confirmed that the phenomenon can be suppressed by lowering the density of the trap levels or the minority carrier lifetime of the bulk wafer","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"219 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117057218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Fully integrated driver power supply for insulated gate transistors 完全集成的驱动电源，用于绝缘栅晶体管
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666151
N. Rouger, J. Crebier, R. Mitova, L. Aubard, C. Schaeffer
{"title":"Fully integrated driver power supply for insulated gate transistors","authors":"N. Rouger, J. Crebier, R. Mitova, L. Aubard, C. Schaeffer","doi":"10.1109/ISPSD.2006.1666151","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666151","url":null,"abstract":"Nowadays, MOSFET and IGBT driver supplies are a great source of interest, mainly for two reasons: the need for high side transistor isolated driver supplies (mid and high power) and massive, low cost, MOSFET applications (home appliance). In order to remove the external floating power supply, necessary to power supply the driver of an insulated gate transistor (especially when its source is floating or at high voltage levels), we purpose to detail, in this article, a solution that integrates, in the same substrate, few supplementary parts, and as consequence, allows to create the necessary floating power supply. The added circuit operational characteristics have already been outlined and a special focus will be made on its full integration. Firstly, the paper recalls how its specific operating mode impacts on the design of its components. Then the technological and electrical compatibilities among all parts, within the main switch, will be outlined. After that, simulation and practical results are shown, according to that with no complex process flow modification, a floating power supply for insulated gate transistor is created (for static and dynamic operations)","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127357699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
The Optimized Monolithic Fault Protection Circuit for the Soft-shutdown behavior of 600V PT-IGBT by employing a New Blanking Filter 采用新型消隐滤波器优化的600V PT-IGBT单片故障保护电路的软关机行为
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666103
I. Ji, Young-Hwan Choi, Soo-Seong Kim, Kwang-Hoon Oh, M. Han
{"title":"The Optimized Monolithic Fault Protection Circuit for the Soft-shutdown behavior of 600V PT-IGBT by employing a New Blanking Filter","authors":"I. Ji, Young-Hwan Choi, Soo-Seong Kim, Kwang-Hoon Oh, M. Han","doi":"10.1109/ISPSD.2006.1666103","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666103","url":null,"abstract":"We have proposed an optimization method of fault protection circuit, which uses the floating p-well voltage detection, of IGBT by employing a novel blanking filter. The floating p-well capacitor and gate resistor, which filter the false detection during the normal switching period, cause the pull-down MOSFET to lower the gate voltage of the IGBT softly. The experimental results show the soft-shutdown behavior of the IGBT with the optimized protection circuit during the fault condition. We have also investigated the switching characteristics by using the measurement and 2-dimensional numerical simulation","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123551456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
650V SOI LIGBT for Switch-Mode Power Supply Application 用于开关电源的650V SOI灯
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666145
T. Letavic, J. Petruzzello, J. Claes, P. Eggenkamp, E. Janssen, A. B. van der Wal
{"title":"650V SOI LIGBT for Switch-Mode Power Supply Application","authors":"T. Letavic, J. Petruzzello, J. Claes, P. Eggenkamp, E. Janssen, A. B. van der Wal","doi":"10.1109/ISPSD.2006.1666145","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666145","url":null,"abstract":"This paper presents a thin-layer high voltage silicon-on-insulator conductivity modulated device which has been optimized for use within integrated switch mode power supply applications. The device contains a linearly-graded charge profile in the drift region, and the fast-switching LIGBT can be used at current densities which are at least a factor-of-two greater than the SOI LDMOS of equivalent breakdown voltage (LIGBT BVds 650V/Rsp 4 ohm mm2). A device failure mechanism which occurs during shorted-winding SMPS transients unique to thin-layer devices has been documented, and device protection circuitry has been developed to provide a transient current limit mechanism within the high voltage device. The electrical characteristics of the protected conductivity modulated thin-layer SOI high voltage device are comparable to state-of-the-art discrete components, and as such this process technology provides a monolithic alternative for miniaturization and integration of switch mode power supply topologies","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122474648","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
Power Cycling at High Temperature Swings of Modules with Low Temperature Joining Technique 采用低温连接技术的模块高温振荡下的功率循环
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666110
R. Amro, J. Lutz, J. Rudzki, R. Sittig, M. Thoben
{"title":"Power Cycling at High Temperature Swings of Modules with Low Temperature Joining Technique","authors":"R. Amro, J. Lutz, J. Rudzki, R. Sittig, M. Thoben","doi":"10.1109/ISPSD.2006.1666110","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666110","url":null,"abstract":"Standard packaging and interconnection technologies limit the maximal junction temperature (Tjmax) to about 150degC at present. This restriction is caused by the limited power cycling capabilities of Al bond wires and of soft solder joints. Important applications of power devices, however, require operating temperatures of 175degC or even 200degC. To evaluate the suitability of the low temperature joining technique (LTJT) for future module set-up, test samples were prepared and investigated. Already the replacement of only the chip-to-substrate solder joint (one-sided LTJT) improved the power cycling capability at DeltaTj=130K five times or at a DeltaTj=156K ten times compared to the expected capability of soldered and wire bonded devices at these conditions. Application of LTJT to top side chip connections also, i.e. additional replacement of bond wires by silver stripes joined by LTJT (double-sided LTJT), yielded a further increase of power cycling capability","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129488447","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 48
RF diamond MISFETs using surface accumulation layer 采用表面积累层的射频金刚石misfet
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666073
K. Hirama, T. Koshiba, K. Yohara, H. Takayanagi, S. Yamauchi, M. Satoh, H. Kawarada
{"title":"RF diamond MISFETs using surface accumulation layer","authors":"K. Hirama, T. Koshiba, K. Yohara, H. Takayanagi, S. Yamauchi, M. Satoh, H. Kawarada","doi":"10.1109/ISPSD.2006.1666073","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666073","url":null,"abstract":"Diamond metal-insulator-semiconductor field-effect-transistors (MISFETs) utilizing a hole accumulation layer have been fabricated on a hydrogen-terminated (H-terminated) diamond surface. The highest cut-off frequency (fT) of 30 GHz and the maximum frequency of oscillation (fmax) of 60 GHz were obtained in the 0.35 mum gate diamond MISFET. RF power operations of diamond MISFETs were demonstrated for the first time. In RF power operation, the high power density of 2.14 W/mm was obtained at 1 GHz","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126786231","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Successful Development of 1.2 kV 4H-SiC MOSFETs with the Very Low On-Resistance of 5 mΩcm2 1.2 kV 4H-SiC mosfet的成功开发，导通电阻为5 mΩcm2
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666121
N. Miura, K. Fujihira, Y. Nakao, T. Watanabe, Y. Tarui, S. Kinouchi, M. Imaizumi, T. Oomori
{"title":"Successful Development of 1.2 kV 4H-SiC MOSFETs with the Very Low On-Resistance of 5 mΩcm2","authors":"N. Miura, K. Fujihira, Y. Nakao, T. Watanabe, Y. Tarui, S. Kinouchi, M. Imaizumi, T. Oomori","doi":"10.1109/ISPSD.2006.1666121","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666121","url":null,"abstract":"4H-SiC MOSFETs comprised of a miniaturized unit cell structure were fabricated. The epilayer channel configuration was employed to effectively improve the MOSFET electrical characteristics. A specific on-resistance of 5 mOmegacm2 with a stable avalanche breakdown of 1.35 kV was successfully recorded. Temperature dependence of the Ron,sp examined and the Ron,sp exhibited still low value of 8.5 mOmegacm2 at 150 degC . The SiC-MOSFETs were put together with SiC-SBDs to realize prototype SiC power modules. A switching energy loss was significantly reduced by employing the SiC module in comparison with a Si-IGBT/Si-FWD module. A three-phase inverter circuit consisted of the SiC module was assembled and stably drove a 3.7 kW/400 V induction motor","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123871045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Mechanical stress dependence of power device electrical characteristics 动力装置电气特性的机械应力依赖性
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1541/IEEJIAS.128.577
H. Tanaka, K. Hotta, S. Kuwano, M. Usui, M. Ishiko
{"title":"Mechanical stress dependence of power device electrical characteristics","authors":"H. Tanaka, K. Hotta, S. Kuwano, M. Usui, M. Ishiko","doi":"10.1541/IEEJIAS.128.577","DOIUrl":"https://doi.org/10.1541/IEEJIAS.128.577","url":null,"abstract":"This paper describes how mechanical stress affects the electrical characteristics of a power device, depending on the surface structure of the device or the device type. Experimental results show that devices in which the current flow direction is vertical to the substrate, such as trench structure devices, are affected the least by mechanical stress","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123235393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Investigation of carrier streaming effect for the low spike fast IGBT turn-off 低尖峰快速IGBT关断的载波流效应研究
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666099
Y. Onozawa, M. Otsuki, Y. Seki
{"title":"Investigation of carrier streaming effect for the low spike fast IGBT turn-off","authors":"Y. Onozawa, M. Otsuki, Y. Seki","doi":"10.1109/ISPSD.2006.1666099","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666099","url":null,"abstract":"This paper describes the investigation of the IGBT turn-off phenomena especially focused on the di/dt controlling in order to suppress the spike voltage. The design concepts for improvement of the trade-off relationship between the turn-off power dissipation and the spike voltage are represented. The new turn-off di/dt control method, the combination of the smaller gate resistance and controlling the collector injection efficiency, has been able to realize about 30% reduction in the turn-off energy compared to the conventional method, under the condition of the same spike voltage","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121469662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Fabrication of AlGaN/GaN HFET with a high breakdown voltage of over 1050 V 击穿电压超过1050 V的AlGaN/GaN HFET的制备
2006 IEEE International Symposium on Power Semiconductor Devices and IC's Pub Date : 2006-06-04 DOI: 10.1109/ISPSD.2006.1666135
S. Yoshida, Jiang Li, H. Takehara, H. Kambayashi, N. Ikeda
{"title":"Fabrication of AlGaN/GaN HFET with a high breakdown voltage of over 1050 V","authors":"S. Yoshida, Jiang Li, H. Takehara, H. Kambayashi, N. Ikeda","doi":"10.1109/ISPSD.2006.1666135","DOIUrl":"https://doi.org/10.1109/ISPSD.2006.1666135","url":null,"abstract":"We performed an AlGaN/GaN Schottky barrier diode (SBD) with a high breakdown voltage of over 1000V on Si (111) substrate. An AlGaN/GaN heterostructure without any crack was realized on a Si (111) substrate using a metalorganic chemical vapor deposition (MOCVD). We also fabricated an AlGaN/GaN heterojunction field effect transistor (HFET) using an AlGaN/GaN heterostructure on a Si (111) substrate. The fabrication process was the same as SBD. The gate length and width were 2000 nm and 0.4 mm, respectively. The distance of gate and drain was 15000 nm. The off-state breakdown voltage of the HFET was over 1050V","PeriodicalId":198443,"journal":{"name":"2006 IEEE International Symposium on Power Semiconductor Devices and IC's","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133015962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
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