发布求助
文献互助 智能选刊 最新文献

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.最新文献

筛选
英文 中文
SiGe pin-photodetectors integrated on silicon substrates for optical fiber links 集成在硅衬底上用于光纤链路的SiGe引脚光电探测器
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234341
G. Wohl, C. Parry, Erich Kasper, M. Jutzi, Manfred Berroth
{"title":"SiGe pin-photodetectors integrated on silicon substrates for optical fiber links","authors":"G. Wohl, C. Parry, Erich Kasper, M. Jutzi, Manfred Berroth","doi":"10.1109/ISSCC.2003.1234341","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234341","url":null,"abstract":"100% Ge pin-photodetectors grown on SiGe strain relaxed buffer (SRB) layers are presented, For integrated detectors the SRB layer growth as well as the subsequent SiGe photodiode technology processing must be compatible with standard CMOS technology. DC photoresponsivities of 145 mA/W at 1.3 /spl mu/m and 25 mA/W at 1.55 /spl mu/m can be achieved. In first experiments the 100% Ge pin-photodetector exhibits an RC limited 3-dB opto-electrical bandwidth of 0.9 GHz.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120935448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless 用于3GPP-HSDPA移动无线的24Mb/s基数-4 logMAP turbo解码器
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234244
M. Bickerstaff, Linda Davis, Charles Thomas, David Garrett, Chris Nicol
{"title":"A 24Mb/s radix-4 logMAP turbo decoder for 3GPP-HSDPA mobile wireless","authors":"M. Bickerstaff, Linda Davis, Charles Thomas, David Garrett, Chris Nicol","doi":"10.1109/ISSCC.2003.1234244","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234244","url":null,"abstract":"A 24Mb/s 3GPP-HSDPA radix-4 logMAP turbo decoder is designed for 3G data terminals. It features an approximate radix-4 logsum circuit to achieve 145MHz operation. Power is reduced using 1/2-iteration early termination and extrinsics are interleaved in companded format. The decoder core is 14.5mm/sup 2/ in 0.18/spl mu/m CMOS.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126529247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 147
A 1 Gb multilevel AG-AND-type flash memory with 10 MB/s programming throughput for mass storage application 1gb多级ag - and型闪存，具有10mb /s的编程吞吐量，适用于大容量存储应用
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234305
K. Yoshida, O. Tsuchiya, Y. Yamaguchi, J. Kishimoto, Y. Ikeda, S. Narumi, Y. Takase, K. Furusawa, K. Izawa, T. Yoshitake, T. Kobayashi, H. Kurata, M. Kanemitsu
{"title":"A 1 Gb multilevel AG-AND-type flash memory with 10 MB/s programming throughput for mass storage application","authors":"K. Yoshida, O. Tsuchiya, Y. Yamaguchi, J. Kishimoto, Y. Ikeda, S. Narumi, Y. Takase, K. Furusawa, K. Izawa, T. Yoshitake, T. Kobayashi, H. Kurata, M. Kanemitsu","doi":"10.1109/ISSCC.2003.1234305","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234305","url":null,"abstract":"A 1 Gb multilevel flash memory is fabricated in a 0.13 /spl mu/m CMOS process. The chip area of 95 mm/sup 2/ is achieved using AG-AND-type cells with a multilevel program cell technique and compact write-buffer. By use of constant-charge-injection programming and multi-bank operation, high-speed programming throughput of 10 MB/s achieved.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126345331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A current-saving match-line sensing scheme for content-addressable memories 一种内容可寻址存储器的节流匹配线传感方案
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234309
I. Arsovski, A. Sheikholeslami
{"title":"A current-saving match-line sensing scheme for content-addressable memories","authors":"I. Arsovski, A. Sheikholeslami","doi":"10.1109/ISSCC.2003.1234309","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234309","url":null,"abstract":"A match-line sensing scheme that reduces power consumption in content-addressable memories by dynamically allocating less power to match-lines with more mismatches is described. This scheme is implemented in a 256/spl times/144 bit CAM using 1.2 V 0.13 /spl mu/m CMOS achieving a 2 ns search time at 1.3 fJ/bit/search.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"23 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126049207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
40Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120nm CMOS 120nm CMOS的40Gb/s 2:1多路复用器和1:2解路复用器
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234328
D. Kehrer, H. Wohlmuth, H. Knapp, M. Wurzer, A. Scholtz
{"title":"40Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120nm CMOS","authors":"D. Kehrer, H. Wohlmuth, H. Knapp, M. Wurzer, A. Scholtz","doi":"10.1109/ISSCC.2003.1234328","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234328","url":null,"abstract":"A 40Gb/s 2:1 multiplexer in 120nm 1.2V CMOS uses inductive peaking and output series inductor. A companion 1:2 demultiplexer is also described.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126850450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A continuous-time /spl Sigma//spl Delta/ modulator with 88dB dynamic range and 1.1MHz signal bandwidth 连续时间/spl Sigma//spl Delta/调制器，动态范围为88dB，信号带宽为1.1MHz
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234208
S. Yan, E. Sánchez-Sinencio
{"title":"A continuous-time /spl Sigma//spl Delta/ modulator with 88dB dynamic range and 1.1MHz signal bandwidth","authors":"S. Yan, E. Sánchez-Sinencio","doi":"10.1109/ISSCC.2003.1234208","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234208","url":null,"abstract":"A baseband continuous-time multi-bit /spl Sigma//spl Delta/ modulator achieves 88dB dynamic range over a 1.1MHz signal bandwidth consuming 62mW from a 3.3V supply. Excess loop delay encountered in conventional continuous-time modulators is eliminated by the proposed architecture. Clock-jitter sensitivity is considerably reduced compared with prior designs.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134190554","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
10GHz clock distribution using coupled standing-wave oscillators 使用耦合驻波振荡器的10GHz时钟分布
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234369
F. O’Mahony, C. Yue, M. Horowitz, S.S. Wong
{"title":"10GHz clock distribution using coupled standing-wave oscillators","authors":"F. O’Mahony, C. Yue, M. Horowitz, S.S. Wong","doi":"10.1109/ISSCC.2003.1234369","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234369","url":null,"abstract":"A global clock network comprised of coupled, standing-wave oscillators is prototyped in a 0.18/spl mu/m 6M CMOS process. The clock network operates from 9.8 to 10.5 GHz with 0.6ps skew and contributes only 0.5ps jitter when referencing a clock source with 1.4ps rms jitter.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134370940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 41
A variable-kernel flash-convolution image filtering processor 可变核闪存卷积图像滤波处理器
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234391
K. Ito, M. Ogawa, T. Shibata
{"title":"A variable-kernel flash-convolution image filtering processor","authors":"K. Ito, M. Ogawa, T. Shibata","doi":"10.1109/ISSCC.2003.1234391","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234391","url":null,"abstract":"A VLSI image filtering processor is designed for single-clock-cycle kernel convolution employing quaternary-tile pixel-data mapping and variable data masking techniques. The concept has been verified by a test chip fabricated in 0.18/spl mu/m CMOS 5M technology. Without pipelining the IC operates at 50MHz with a 1.8V supply.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132569306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 700 mW CMOS line driver for ADSL central office applications 用于ADSL中继局应用的700mw CMOS线路驱动器
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234363
A. Bicakci, Chun-Sup Kim, Sang-Soo Lee, C. Conroy
{"title":"A 700 mW CMOS line driver for ADSL central office applications","authors":"A. Bicakci, Chun-Sup Kim, Sang-Soo Lee, C. Conroy","doi":"10.1109/ISSCC.2003.1234363","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234363","url":null,"abstract":"A dual-channel analog front-end for ANSI/ETSI standards compliant VDSL in 0.25/0.5/spl mu/m 1P 5M CMOS is presented. The chip includes a non-linearity cancelling multi-path line driver achieving -76dBc 3rd harmonic distortion at 12MHz, a 75mW continuous-time multi-bit 3rd-order self-calibrating /spl Sigma//spl Delta/ ADC, a 14b current-steering DAC with PSD mask post filter, a 0-35dB variable-gain amplifier with adjustable hybrid, and a 12ps jitter LC PLL.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132040703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Scalable sub-10ps skew global clock distribution for a 90nm multi-GHz IA microprocessor 用于90nm多ghz IA微处理器的可扩展sub-10ps倾斜全局时钟分布
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI: 10.1109/ISSCC.2003.1234329
N. Bindal, T. Kelly, N. Velastegui, K.L. Wong
{"title":"Scalable sub-10ps skew global clock distribution for a 90nm multi-GHz IA microprocessor","authors":"N. Bindal, T. Kelly, N. Velastegui, K.L. Wong","doi":"10.1109/ISSCC.2003.1234329","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234329","url":null,"abstract":"A three-level clock distribution design for a next generation IA microprocessor is implemented in a 1.2V, 90nm process that scales to a 5GHz range. It achieves sub-10ps global clock uncertainty and addresses in-die variation, RLC delay matching, and scalability with die size and process issues without additional clock jitter or layout area. Risk management of practical constraints due to schedule, changing floor plan, loading and process are discussed.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"400 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132337217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信