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120nm CMOS的40Gb/s 2:1多路复用器和1:2解路复用器

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-02-09 DOI:10.1109/ISSCC.2003.1234328
D. Kehrer, H. Wohlmuth, H. Knapp, M. Wurzer, A. Scholtz
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引用次数: 16

摘要

120nm 1.2V CMOS的40Gb/s 2:1多路复用器采用感应峰值和输出串联电感。还描述了配套的1:2解复用器。
本文章由计算机程序翻译，如有差异，请以英文原文为准。
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40Gb/s 2:1 multiplexer and 1:2 demultiplexer in 120nm CMOS
A 40Gb/s 2:1 multiplexer in 120nm 1.2V CMOS uses inductive peaking and output series inductor. A companion 1:2 demultiplexer is also described.
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2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
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