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2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.最新文献

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A 2.5-10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization 一种2.5-10Gb/s的CMOS收发器，采用交替边缘采样相位检测，用于环路特性稳定
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-27 DOI: 10.1109/JSSC.2003.818290
Bong-Joon Lee, Moon-Sang Hwang, Sang-Hyun Lee, D. Jeong
{"title":"A 2.5-10Gb/s CMOS transceiver with alternating edge sampling phase detection for loop characteristic stabilization","authors":"Bong-Joon Lee, Moon-Sang Hwang, Sang-Hyun Lee, D. Jeong","doi":"10.1109/JSSC.2003.818290","DOIUrl":"https://doi.org/10.1109/JSSC.2003.818290","url":null,"abstract":"A 2.5 to 10 Gb/s CMOS transceiver in 0.18 /spl mu/m CMOS dissipates 540 mW from a 1.8 V supply with a BER better than 10/sup -12/. CDR loop characteristics are stabilized across various jitter environments with small hardware overhead using an alternating edge sampling phase detector.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132942774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write 一个1.8 V 128 Mb 125 MHz多级单元闪存具有灵活的读同时写
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-27 DOI: 10.1109/ISSCC.2003.1234304
D. Elmhurst, R. Bains, T. Bressie, C. Bueb, E. Carrieri, B. Chauhan, N. Chrisman, M. Dayley, R. De Luna, K. Fan, M. Goldman, P. Govindu, A. Huq, M. Khandaker, J. Kreifels, S. Krishnamachari, P. Lavapie, K. Loe, T. Ly, F. Marvin, R. Melcher, S. Monasa, Q. Nguyen, B. Pathak, A. Proescholdt, T. Rahman, B. Srinivasan, R. Sundaram, P. Walimbe, D. Ward, D. Zeng, H. Zhang
{"title":"A 1.8 V 128 Mb 125 MHz multi-level cell flash memory with flexible read while write","authors":"D. Elmhurst, R. Bains, T. Bressie, C. Bueb, E. Carrieri, B. Chauhan, N. Chrisman, M. Dayley, R. De Luna, K. Fan, M. Goldman, P. Govindu, A. Huq, M. Khandaker, J. Kreifels, S. Krishnamachari, P. Lavapie, K. Loe, T. Ly, F. Marvin, R. Melcher, S. Monasa, Q. Nguyen, B. Pathak, A. Proescholdt, T. Rahman, B. Srinivasan, R. Sundaram, P. Walimbe, D. Ward, D. Zeng, H. Zhang","doi":"10.1109/ISSCC.2003.1234304","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234304","url":null,"abstract":"A 128 Mb flash memory with a two bit-per-cell design on a 0.13 /spl mu/m technology achieves a random access time of 55 ns and 125 MHz synchronous operation. The design incorporates a flexible multi-partition memory architecture which allows a program or erase operation to occur in one partition of the memory while bursting data out of another partition. The die is 27.3 mm/sup 2/ with a 0.154 /spl mu/m/sup 2/ cell size.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117201009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Dynamic-sleep transistor and body bias for active leakage power control of microprocessors 微处理器有源泄漏功率控制的动态睡眠晶体管和体偏置
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-27 DOI: 10.1109/JSSC.2003.818291
J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, S. Borkar, V. De
{"title":"Dynamic-sleep transistor and body bias for active leakage power control of microprocessors","authors":"J. Tschanz, S. Narendra, Y. Ye, B. Bloechel, S. Borkar, V. De","doi":"10.1109/JSSC.2003.818291","DOIUrl":"https://doi.org/10.1109/JSSC.2003.818291","url":null,"abstract":"Sleep transistors and body bias are used to control active leakage for a 32b integer execution core implemented in a 100nm dual V, CMOS technology. A PMOS sleep transistor degrades performance by 4% but offers 20/spl times/ leakage reduction which is further improved with body bias. Time constants for leakage convergence range from 30ns to 300ns allowing 9-44% power savings for idle periods greater than 100 clock cycles.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131868119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 317
A 32Mb chain FeRAM with segment/stitch array architecture 32Mb链FeRAM，分段/针阵结构
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-27 DOI: 10.1109/ISSCC.2003.1234302
S. Shiratake, T. Miyakawa, Y. Takeuchi, R. Ogiwara, M. Kamoshida, K. Hoya, K. Oikawa, T. Ozaki, I. Kunishima, K. Yamakawa, S. Sugimoto, D. Takashima, H. Joachim, N. Rehm, J. Wohlfahrt, N. Nagel, G. Beitel, M. Jacob, T. Roehr
{"title":"A 32Mb chain FeRAM with segment/stitch array architecture","authors":"S. Shiratake, T. Miyakawa, Y. Takeuchi, R. Ogiwara, M. Kamoshida, K. Hoya, K. Oikawa, T. Ozaki, I. Kunishima, K. Yamakawa, S. Sugimoto, D. Takashima, H. Joachim, N. Rehm, J. Wohlfahrt, N. Nagel, G. Beitel, M. Jacob, T. Roehr","doi":"10.1109/ISSCC.2003.1234302","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234302","url":null,"abstract":"A 96mm/sup 2/, 32Mb chain FeRAM in 0.20/spl mu/m 3M CMOS and stacked capacitor technology is described. Cell efficiency of 65.6% is realized by compact memory cell structure and segment/stitch WL architecture. The word line power-on/off sequence protects the data from startup noise. A 3/spl mu/A standby current bias generator and compatible access mode SRAM are implemented for mobile applications.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129679126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-27 DOI: 10.1109/JSSC.2003.818137
Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeonghyu Yang, Kwon-Il Sohn, Sung-Tae Kim, I. Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, H. Byun
{"title":"A 1.2 V 1.5 Gb/s 72 Mb DDR3 SRAM","authors":"Uk-Rae Cho, Tae-Hyoung Kim, Yong-Jin Yoon, Jong-Cheol Lee, Dae-Gi Bae, Nam-Seog Kim, Kang-Young Kim, Young-Jae Son, Jeonghyu Yang, Kwon-Il Sohn, Sung-Tae Kim, I. Lee, Kwang-Jin Lee, Tae-Gyoung Kang, Su-Chul Kim, Kee-Sik Ahn, H. Byun","doi":"10.1109/JSSC.2003.818137","DOIUrl":"https://doi.org/10.1109/JSSC.2003.818137","url":null,"abstract":"A 1.2 V 72 Mb DDR3 SRAM in a 0.10 /spl mu/m CMOS process achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines reduce the power dissipation and the number of data lines by half. Clocks phase-shifted by 0/spl deg/, 90/spl deg/ and 270/spl deg/ are generated by clock adjustment circuits. On-chip input termination with linearity of /spl plusmn/4.1% is developed to improve signal integrity at higher data rates.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128624426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors 16.7 fA/cell tunnel- suppressed 16mb SRAM，用于处理宇宙射线引起的多重错误
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-27 DOI: 10.1109/ISSCC.2003.1234308
Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, K. Ishibashi
{"title":"16.7 fA/cell tunnel-leakage-suppressed 16 Mb SRAM for handling cosmic-ray-induced multi-errors","authors":"Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe, K. Ishibashi","doi":"10.1109/ISSCC.2003.1234308","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234308","url":null,"abstract":"A 16 Mb SRAM based on an electric-field-relaxed scheme and an alternate error checking and correction architecture for handling cosmic-ray-induced multi-errors is realized in 0.13 /spl mu/m CMOS technology. The IC has a 16.7 fA/cell standby current, a cell size of 2.06 /spl mu/m/sup 2/ and a 99.5% smaller SER.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124142926","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 102
A 2/spl times/ load/store pipe for a low-power 1GHz embedded processor 用于低功耗1GHz嵌入式处理器的2/spl倍/加载/存储管道
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-27 DOI: 10.1109/JSSC.2003.818296
Zongjian Chen, D. Murray, S. Nishimoto, M. Pearce, M. Oyker, D. Rodriguez, R. Rogenmoser, Dongwook Suh, E. Supnet, V. V. Kaenel, G. Yiu
{"title":"A 2/spl times/ load/store pipe for a low-power 1GHz embedded processor","authors":"Zongjian Chen, D. Murray, S. Nishimoto, M. Pearce, M. Oyker, D. Rodriguez, R. Rogenmoser, Dongwook Suh, E. Supnet, V. V. Kaenel, G. Yiu","doi":"10.1109/JSSC.2003.818296","DOIUrl":"https://doi.org/10.1109/JSSC.2003.818296","url":null,"abstract":"The load/store pipe in an embedded processor is clocked at 2/spl times/ the processor clock frequency. It sustains two load or store operations per core clock cycle with zero load-to-use issue latency. The design is implemented in 0.13/spl mu/m 7M CMOS process and dissipates between 650 and 1090mW for core clock frequencies between 600MHz and 1GHz.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115507612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A VLIW processor with reconfigurable instruction set for embedded applications 具有可重构指令集的嵌入式VLIW处理器
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-27 DOI: 10.1109/JSSC.2003.818292
Andrea Lodi, M. Toma, F. Campi, A. Cappelli, R. Canegallo, R. Guerrieri
{"title":"A VLIW processor with reconfigurable instruction set for embedded applications","authors":"Andrea Lodi, M. Toma, F. Campi, A. Cappelli, R. Canegallo, R. Guerrieri","doi":"10.1109/JSSC.2003.818292","DOIUrl":"https://doi.org/10.1109/JSSC.2003.818292","url":null,"abstract":"A RISC VLIW processor implements dynamic instruction set extension integrating a pipelined, run-time reconfigurable datapath. A 0.18 /spl mu/m 6M CMOS chip prototype achieves energy consumption reduction up to 90% and time reduction of 13/spl times/ on a signal processing algorithm benchmark. The IC contains 12M transistors and dissipates 120 mW at 80 MHz from a 1.8 V supply.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126924743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 159
Differential 4-tap and 7-tap transverse filters in SiGe for 10Gb/s multimode fiber optic link equalization 用于10Gb/s多模光纤链路均衡的SiGe差分4抽头和7抽头横向滤波器
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-20 DOI: 10.1109/ISSCC.2003.1234257
H. Wu, J. Tierno, P. Pepeljugoski, J. Schaub, S. Gowda, J. Kash, A. Hajimiri
{"title":"Differential 4-tap and 7-tap transverse filters in SiGe for 10Gb/s multimode fiber optic link equalization","authors":"H. Wu, J. Tierno, P. Pepeljugoski, J. Schaub, S. Gowda, J. Kash, A. Hajimiri","doi":"10.1109/ISSCC.2003.1234257","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234257","url":null,"abstract":"Differential 4-tap and 7-tap transverse filters are designed in a 0.18/spl mu/m SiGe BiCMOS technology for equalization of 10Gb/s multimode fiber optic signals. The 7-tap equalizer reduced the ISI of a 10Gb/s signal received through 300m of 50/spl mu/m noncompliant next generation multimode fiber from 4.2dB to 0.8dB. The circuit dissipates 40mW from a 3.3V supply.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125328801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
A batteryless wireless system uses ambient heat with a reversible-power-source compatible CMOS/SOI DC-DC converter 无电池无线系统通过可逆电源兼容的CMOS/SOI DC-DC转换器利用环境热量
2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-20 DOI: 10.1109/ISSCC.2003.1234348
T. Douseki, Y. Yoshida, F. Utsunomiya, N. Itoh, N. Hama
{"title":"A batteryless wireless system uses ambient heat with a reversible-power-source compatible CMOS/SOI DC-DC converter","authors":"T. Douseki, Y. Yoshida, F. Utsunomiya, N. Itoh, N. Hama","doi":"10.1109/ISSCC.2003.1234348","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234348","url":null,"abstract":"A 1mW, self-powered wireless system that utilizes ambient heat is described. A switched-capacitor DC-DC converter composed of fully-depleted SOI MOSFETs and a microthermoelectric module makes use of such heat possible. An experimental 300MHz band short-range wireless transmitter transmits from a distance of 5m using only heat from a hand or from water. The chip is fabricated in a 0.8/spl mu/m fully-depleted SOI process.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121938380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
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