Andrea Lodi, M. Toma, F. Campi, A. Cappelli, R. Canegallo, R. Guerrieri
{"title":"A VLIW processor with reconfigurable instruction set for embedded applications","authors":"Andrea Lodi, M. Toma, F. Campi, A. Cappelli, R. Canegallo, R. Guerrieri","doi":"10.1109/JSSC.2003.818292","DOIUrl":null,"url":null,"abstract":"A RISC VLIW processor implements dynamic instruction set extension integrating a pipelined, run-time reconfigurable datapath. A 0.18 /spl mu/m 6M CMOS chip prototype achieves energy consumption reduction up to 90% and time reduction of 13/spl times/ on a signal processing algorithm benchmark. The IC contains 12M transistors and dissipates 120 mW at 80 MHz from a 1.8 V supply.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-10-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"159","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/JSSC.2003.818292","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 159
Abstract
A RISC VLIW processor implements dynamic instruction set extension integrating a pipelined, run-time reconfigurable datapath. A 0.18 /spl mu/m 6M CMOS chip prototype achieves energy consumption reduction up to 90% and time reduction of 13/spl times/ on a signal processing algorithm benchmark. The IC contains 12M transistors and dissipates 120 mW at 80 MHz from a 1.8 V supply.