A 32Mb chain FeRAM with segment/stitch array architecture

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. Pub Date : 2003-10-27 DOI:10.1109/ISSCC.2003.1234302

S. Shiratake, T. Miyakawa, Y. Takeuchi, R. Ogiwara, M. Kamoshida, K. Hoya, K. Oikawa, T. Ozaki, I. Kunishima, K. Yamakawa, S. Sugimoto, D. Takashima, H. Joachim, N. Rehm, J. Wohlfahrt, N. Nagel, G. Beitel, M. Jacob, T. Roehr

引用次数: 10

Abstract

A 96mm/sup 2/, 32Mb chain FeRAM in 0.20/spl mu/m 3M CMOS and stacked capacitor technology is described. Cell efficiency of 65.6% is realized by compact memory cell structure and segment/stitch WL architecture. The word line power-on/off sequence protects the data from startup noise. A 3/spl mu/A standby current bias generator and compatible access mode SRAM are implemented for mobile applications.

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32Mb链FeRAM，分段/针阵结构

描述了一种96mm/sup /， 32Mb链FeRAM，采用0.20/spl mu/m 3M CMOS和堆叠电容器技术。采用紧凑的存储单元结构和段/针结构实现了65.6%的单元效率。字线上/下电顺序保护数据不受启动噪声的影响。3/spl mu/A备用偏置电流发生器和兼容的访问模式SRAM实现了移动应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.

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