2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.最新文献

筛选
英文 中文
A 1.9GHz image-reject front-end with automatic tuning in a 0.15/spl mu/m CMOS technology 采用0.15/spl mu/m CMOS技术的自动调谐1.9GHz图像抑制前端
M. H. Koroglu, P. Allen
{"title":"A 1.9GHz image-reject front-end with automatic tuning in a 0.15/spl mu/m CMOS technology","authors":"M. H. Koroglu, P. Allen","doi":"10.1109/ISSCC.2003.1234294","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234294","url":null,"abstract":"A 1.9GHz front-end consists of an LNA, an image-reject notch filter with automatic frequency and Q tuning circuits, and a down-conversion mixer. Implemented in a 0.15/spl mu/m CMOS process, the 0.45mm/sup 2/ front-end achieves 5.4dB noise figure, -12dBm IIP3 and consumes 19mW from 1.5V supply.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130445216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS 一个20gs /s的8b ADC,内存为1mb,采用0.18 /spl mu/m CMOS
K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, A. Montijo
{"title":"A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS","authors":"K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, A. Montijo","doi":"10.1109/ISSCC.2003.1234315","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234315","url":null,"abstract":"A 20 GS/s 8-bit ADC achieves a bandwidth of 6 GHz in 0.18 /spl mu/m CMOS. The implementation uses 80 time-interleaved current-mode pipeline sub-ADCs and stores data at 20 GB/s into a 1 MB on-chip memory. The ADC is packaged with a BiCMOS input buffer chip in a 438-ball BGA, and total power consumption is 10 W.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116748609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 138
A fully-integrated 0.13/spl mu/m CMOS mixed-signal SoC for DVD player applications 一个完全集成的0.13/spl μ m CMOS混合信号SoC,用于DVD播放器应用
Koji Okamoto, T. Morie, A. Yamamoto, Kouichi Nagano, K. Sushihara, H. Nakahira, Ryusuke Horibe, Kazutoshi Aida, Toshihiko Takahashi, Minoru Ochiai, Akinobu Soneda, T. Kakiage, Tamaki Iwasaki, Hiroshi Taniuchi, T. Shibata, Takahiro Ochi, Masao Takiguchi, Takashi Yamamoto, Tadayoshi Seike, A. Matsuzawa
{"title":"A fully-integrated 0.13/spl mu/m CMOS mixed-signal SoC for DVD player applications","authors":"Koji Okamoto, T. Morie, A. Yamamoto, Kouichi Nagano, K. Sushihara, H. Nakahira, Ryusuke Horibe, Kazutoshi Aida, Toshihiko Takahashi, Minoru Ochiai, Akinobu Soneda, T. Kakiage, Tamaki Iwasaki, Hiroshi Taniuchi, T. Shibata, Takahiro Ochi, Masao Takiguchi, Takashi Yamamoto, Tadayoshi Seike, A. Matsuzawa","doi":"10.1109/JSSC.2003.818131","DOIUrl":"https://doi.org/10.1109/JSSC.2003.818131","url":null,"abstract":"A mixed-signal SoC for DVD applications is designed in 0.13/spl mu/m 1P 6M CMOS. One DSP, two 32b RISC CPUs, three dedicated processing units, PRML read channel with an analog front end (AFE) and several other subsystems are integrated on the same die. The AFE contains a 5th-order G/sub m/-C filter and over 66dB C/N. The SoC contains 24M transistors in a 64mm/sup 2/ die and consumes 1.5W at 40MS/s which corresponds to 1.5/spl times/ DVD playback.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134278733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A SiGe transmitter chipset for CATV video-on-demand systems 用于有线电视视频点播系统的SiGe发射机芯片组
K. Ashby, R. Greene, B. Nise, M. Womac, D. Stout, A. Taddiken
{"title":"A SiGe transmitter chipset for CATV video-on-demand systems","authors":"K. Ashby, R. Greene, B. Nise, M. Womac, D. Stout, A. Taddiken","doi":"10.1109/ISSCC.2003.1234375","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234375","url":null,"abstract":"A 3-chip, 6.5W CATV transmitter for video-on-demand applications is implemented in a 0.5/spl mu/m SiGe BiCMOS process. A 38dBmV IF input at 44MHz or 36.125MHz is upconverted to an output between 50 and 860MHz at a level adjustable between 41 and 58dBmV in <0.1dB steps. The 75/spl Omega/ input return loss is <-25dB and the 75/spl Omega/ output return loss is <-160. The wideband noise floor is <-80dBmV/Hz. Spurious signals in the CATV band are <-60dBc, and phase noise is <-88dBc/Hz at 10kHz offset.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121283453","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator 一种低功耗CMOS蓝牙收发器,带有数字偏移抵消dll的GFSK解调器
Chan-Hong Park, S. Byun, Y. Song, S. Wang, C. Conroy, B. Kim
{"title":"A low power CMOS Bluetooth transceiver with a digital offset canceling DLL-based GFSK demodulator","authors":"Chan-Hong Park, S. Byun, Y. Song, S. Wang, C. Conroy, B. Kim","doi":"10.1109/ISSCC.2003.1234223","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234223","url":null,"abstract":"A 0.18/spl mu/m CMOS Bluetooth IC consumes 33mA in RX mode and 25mA in TX mode. The IC has a DLL-based GFSK demodulator with frequency offset cancellation. The receiver has -78dBm sensitivity at 0.1% BER, and the transmitter delivers a nominal 0dBm power level with 20dB control.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"1 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117317626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 59
1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme 1.27Gb/s/pin 3mW/pin无线超级连接(WSC)接口方案
K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, T. Sakurai
{"title":"1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme","authors":"K. Kanda, D. Antono, K. Ishida, H. Kawaguchi, T. Kuroda, T. Sakurai","doi":"10.1109/ISSCC.2003.1234260","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234260","url":null,"abstract":"A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm/sup 2/. The interface utilizes capacitively coupled contactless minipads, return-to-half-V/sub 00/ signaling and sense amplifying F/F. The measured test chip fabricated in 0.35/spl mu/m CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126878734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 131
A single-chip CMOS Bluetooth transceiver with 1.5MHz IF and direct modulation transmitter 单片CMOS蓝牙收发器,1.5MHz中频和直接调制发射器
H. Ishikuro, M. Hamada, K. Agawa, S. Kousai, H. Kobayashi, D. Nguyen, F. Hatori
{"title":"A single-chip CMOS Bluetooth transceiver with 1.5MHz IF and direct modulation transmitter","authors":"H. Ishikuro, M. Hamada, K. Agawa, S. Kousai, H. Kobayashi, D. Nguyen, F. Hatori","doi":"10.1109/ISSCC.2003.1234222","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234222","url":null,"abstract":"A single-chip Bluetooth transceiver in 0.18/spl mu/m CMOS integrates a direct VCO modulation transmitter and 1.5MHz-IF receiver to reduce power consumption and cost. The receiver achieves a sensitivity of -77dBm and transmitting power of +4dBm.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-07-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115797268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
Perspectives on power-aware electronics 功率感知电子的观点
T. Sakurai
{"title":"Perspectives on power-aware electronics","authors":"T. Sakurai","doi":"10.1109/ISSCC.2003.1234195","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234195","url":null,"abstract":"In the coming ubiquitous-IT society, low-power design is one of the key features at which the VLSI designer should aim. Otherwise, power increase will remain as one of the main obstacles to Moore's law growth. Unless VLSI power is lowered by orders of magnitude, we cannot enjoy the progress that scaling offers. This talk will cover what we now have, and what we should provide in our low-power armory to allow us to cope with ever-increasing leakage loss, as well as dynamic power. The techniques to be presented range over the system, software, circuit, and device levels including interconnect and I/O issues. The novel trend is to examine cooperative approaches between levels such as software-circuit cooperation and circuit-technology cooperation. The biggest challenge that System-on-Chip designers must resolve in the future is the fact that transistors for digital and memory circuits will be more and more leaky as technology generations advance. Approaches to solving this serious problem will be described. Beyond the quest for low-power solutions lies a promising world of ubiquitous VLSI devices and products ranging from \"wireless sensors and tags for everything\" to \"everything-you-must-do mobile terminals\".","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"4 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115674839","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 116
Enabling technologies for disappearing electronics in smart textiles 智能纺织品中消失电子器件的技术
S. Jung, C. Lauterbach, M. Strasser, W. Weber
{"title":"Enabling technologies for disappearing electronics in smart textiles","authors":"S. Jung, C. Lauterbach, M. Strasser, W. Weber","doi":"10.1109/ISSCC.2003.1234347","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234347","url":null,"abstract":"Enabling technologies for 'wearable electronics', such as packaging and interconnect, are the key to the integration of electronics in textiles. A silicon-based micromachined thermoelectric generator chip for energy harvesting from body heat, and an interwoven antenna concept for textile radio frequency identification labels are presented.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115702731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 85
Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications 图像处理器能够以30帧/秒的速度进行无块噪声JPEG2000压缩,适用于数码相机应用
H. Yamauchi, S. Okada, K. Taketa, T. Ohyama, Y. Matsuda, T. Mori, T. Watanabe, Y. Matsuo, Y. Yamada, T. Ichikawa, Y. Matsushita
{"title":"Image processor capable of block-noise-free JPEG2000 compression with 30 frames/s for digital camera applications","authors":"H. Yamauchi, S. Okada, K. Taketa, T. Ohyama, Y. Matsuda, T. Mori, T. Watanabe, Y. Matsuo, Y. Yamada, T. Ichikawa, Y. Matsushita","doi":"10.1109/ISSCC.2003.1234201","DOIUrl":"https://doi.org/10.1109/ISSCC.2003.1234201","url":null,"abstract":"A one-chip image processor for next-generation digital cameras and broadband PDA multimedia mobile phones is described. It is capable of processing JPEG2000 data with 30 frames/s and a 27 MHz operating frequency. The process is fabricated in 0.25 /spl mu/m CMOS and contains 8.5M transistors in a 103 mm/sup 2/ area.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-02-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125346551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信