{"title":"采用0.15/spl mu/m CMOS技术的自动调谐1.9GHz图像抑制前端","authors":"M. H. Koroglu, P. Allen","doi":"10.1109/ISSCC.2003.1234294","DOIUrl":null,"url":null,"abstract":"A 1.9GHz front-end consists of an LNA, an image-reject notch filter with automatic frequency and Q tuning circuits, and a down-conversion mixer. Implemented in a 0.15/spl mu/m CMOS process, the 0.45mm/sup 2/ front-end achieves 5.4dB noise figure, -12dBm IIP3 and consumes 19mW from 1.5V supply.","PeriodicalId":171288,"journal":{"name":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"A 1.9GHz image-reject front-end with automatic tuning in a 0.15/spl mu/m CMOS technology\",\"authors\":\"M. H. Koroglu, P. Allen\",\"doi\":\"10.1109/ISSCC.2003.1234294\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.9GHz front-end consists of an LNA, an image-reject notch filter with automatic frequency and Q tuning circuits, and a down-conversion mixer. Implemented in a 0.15/spl mu/m CMOS process, the 0.45mm/sup 2/ front-end achieves 5.4dB noise figure, -12dBm IIP3 and consumes 19mW from 1.5V supply.\",\"PeriodicalId\":171288,\"journal\":{\"name\":\"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-10-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2003.1234294\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2003.1234294","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.9GHz image-reject front-end with automatic tuning in a 0.15/spl mu/m CMOS technology
A 1.9GHz front-end consists of an LNA, an image-reject notch filter with automatic frequency and Q tuning circuits, and a down-conversion mixer. Implemented in a 0.15/spl mu/m CMOS process, the 0.45mm/sup 2/ front-end achieves 5.4dB noise figure, -12dBm IIP3 and consumes 19mW from 1.5V supply.